Design of new AUTOSAR memory stack for diagnostic message

Hwang, Hyun-Yong; Lee, Jeong‐Hwan; Han, Tae-Man

doi:10.1109/ictc.2012.6387197

Search citation statements

Order By: Relevance

Paper Sections

Select...

Introduction1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2013

2021

Publication Types

Select...

Article1

Other1

Relationship

Self Cite0

Independent2

Authors

Journals

Cited by 2 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…First, the stack of layers makes it more difficult for heat to dissipate and this fact results in severe thermal problems. Second, the low yield of signal TSVs has a great impact on the yield of the whole chip [1]. To solve these problems, designers map applications onto different topologies with the specific objectives.…”

Section: Introductionmentioning

confidence: 99%

3D Networks-on-Chip mapping targeting minimum signal TSVs

Ding

Yang

et al. 2013

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The interlayer communication is optimized, which facilitates reduction of signal TSVs. What's more, the peak temperature is limited by placing IP cores with high power on the layer close to the heat sink. Experimental results indicate that the number of signal TSVs is decreased and that tradeoffs can be made between the number of signal TSVs and peak temperature.

show abstract

Section: Introductionmentioning

confidence: 99%