Design of multi-tasking coprocessor control for Eclipse

Rutten, Martijn J.; Eijndhoven, J.T.J. van; Pol, Evert-Jan D.

doi:10.1145/774814.774818

Cited by 2 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…ECLIPSE provides an architectural framework for on chip CPU and coprocessor communication, combining application configuration flexibility with the efficiency of function specific hardware (coprocessors). [12]. Figure 2 depicts this hardware interface block that separates the computation hardware (coprocessors) from the communication hardware (buses, memory).…”

Section: Eclipse Architecturementioning

confidence: 99%

“…In ECLIPSE task scheduling is distributed [12]; the tasks are scheduled independently by their respective shells. The coprocessors are loosely coupled, implying that within the time-scale that the buffer can bridge, scheduling of tasks on one coprocessor is independent of the instantaneous scheduling of tasks on other coprocessors.…”

Section: Artificial Deadlocks In Eclipsementioning

confidence: 99%

See 1 more Smart Citation

Artificial Deadlock Detection in Process Networks for ECLIPSE

Bharath

Nandy

Bussa

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

View full text Add to dashboard Cite

Kahn Process Network (KPN) is a popular model of computation for describing streaming applications. In a KPN model, processes communicate through unbounded unidirectional FIFOs. When theoretically unbounded FI-FOs are implemented using finite memory, artificial deadlocks can occur due to one or more FIFOs having insufficient sizes. Generally a system designer must be able to make a design time trade-off between execution time and memory usage, preferably using no more memory than required for obtaining a certain execution time. But it is practically impossible to decide at design time, FIFO sizes that are sufficient to run the application without any artificial deadlocks. Hence there is a need for runtime mechanism for handling the artificial deadlock situations in process networks. Existing mechanisms detect artificial deadlocks only after all KPN processes block. This results in excessive blocking of processes and an application that appears to 'hang'. In this paper we present an improved mechanism for early detection of artificial deadlocks and its implementation on ECLIPSE (Extended CPU Local Irregular Processing ArchitecturE), an application domain specific architecture.

show abstract

Section: Eclipse Architecturementioning

confidence: 99%

Section: Artificial Deadlocks In Eclipsementioning

confidence: 99%

Artificial Deadlock Detection in Process Networks for ECLIPSE

Bharath

Nandy

Bussa

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

View full text Add to dashboard Cite

show abstract

“…This saves valuable design effort and design time. After transformation the networks consist of tasks which inter-operate through a platform interface using concepts such as described in [2], [7], [12], and [14]. We apply these transformations on source code such that the resulting code can be used as input for existing silicon and software compilers.…”

Section: Introductionmentioning

confidence: 99%

Multiprocessor mapping of process networks: a JPEG decoding case study

Kock¹

15th International Symposium on System Synthesis, 2002.

View full text Add to dashboard Cite

We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a structured approach for implementing process networks. We use process networks as re-usable and architecture-independent functional specifications. The method facilitates the cost-driven and constraint-driven source code transformation of process networks into architecture-specific implementations in the form of communicating tasks. We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors. We apply three transformations to optimize synchronization rates and data transfers and to exploit data parallelism for this target architecture. We evaluate the impact of the source code transformations and the performance of the resulting implementations in terms of design time, execution time, and code size. The results show that process networks can be implemented quickly and efficiently on embedded multiprocessor systems.

show abstract

Design of multi-tasking coprocessor control for Eclipse

Cited by 2 publications

References 0 publications

Artificial Deadlock Detection in Process Networks for ECLIPSE

Artificial Deadlock Detection in Process Networks for ECLIPSE

Multiprocessor mapping of process networks: a JPEG decoding case study

Contact Info

Product

Resources

About