Multiprocessor mapping of process networks: a JPEG decoding case study

Kock, E.A. de

doi:10.1109/isss.2002.1227154

Cited by 23 publications

(31 citation statements)

References 12 publications

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“…Interested readers are pointed to [80]. The second application is a Philips in-house JPEG decoder from [26]. Regarding this application, we only have the topology information but not the real implementation.…”

Section: Methodsmentioning

confidence: 99%

System-Level Modelling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures

Erbas¹

2006

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Section: Methodsmentioning

confidence: 99%

System-Level Modelling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures

Erbas¹

2006

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“…The case study is performed for JPEG and H263 applications. The descriptions are obtained from [22] and [23] respectively. Both applications are mapped onto a 3 processor platform.…”

Section: A Dse Case Studymentioning

confidence: 99%

Performance evaluation of concurrently executing parallel applications on multi-processor systems

Shabbir

Kumar

Mesman

et al. 2009

2009 International Symposium on Systems, Architectures, Modeling, and Simulation

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Abstract-Multi-processors are increasingly being used in modern embedded systems for reasons of power and speed. These systems have to support a large number of applications and standards, in different combinations, called use-cases. The key challenges are designing efficient systems handling all these usecases; this requires fast exploration of software and hardware alternatives with accurate performance evaluation. In this paper, we present a system-level FPGA-based simulation methodology for performance evaluation of applications on multiprocessor platforms. We observe that for multiple applications sharing an MPSoC platform, dynamic arbitration can cause deadlock in simulation. We use conservative Parallel Discrete Event Simulation (PDES) for simulation of these use-cases. We further note that conservative PDES is inefficient so we present a new PDES methodology that avoids causality errors by detecting them in advance. We call our new approach as smart conservative PDES. It is scalable in the number of use-cases and number of simulated processors and is 15% faster than conservative PDES. We further present results of a case-study of two real life applications. We used our simulation technique to do a design space exploration for optimal buffer space for JPEG and H263 decoders.

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“…This section presents results of a case study regarding the mapping of H263 and JPEG decoder SDF models (described in [12] and [9] respectively) on a three-node MPSoC. Corresponding SDF graphs are shown in Figure 14.…”

Section: Performance Evaluationmentioning

confidence: 99%