Design of Low-Power Sub-2.4 dB Mean NF 5G LNAs Using Forward Body Bias in 22 nm FDSOI

In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization

“…Moreover, the LNA employs techniques to improve gain and input impedance match for wideband operation using two transformers. In [25] (22-nm CMOS SOI), the LNA uses a cascode based topology with an input transformer to enhance the gain, input impedance matching, and noise performance. It should be noted that all the LNAs reported in Table XIII, except [28], which uses a 65-nm CMOS technology similar to the one employed in this work, use more advanced CMOS Silicon-On-Insulator (SOI) technologies of smaller dimensions (lower nodes) than the one used to develop the LNA1, LNA2 and LNA3.…”

“…A finer assessment of the performances of the LNA1 variants shows that the gains are close to 11-dB, which is higher than the ones of the [2], [25], and [27] LNAs. Although the HighG and LowNF variants of the LNA1 attain a higher gain than the LNAs reported in [2], [25], and [27], they consume a little more power (1.5-mW to 4.5-mW). However, the LNA1 LowP variant obtains a gain higher than the LNAs reported in [2], [25], and [27] with less power consumption (2-mW to 5-mW).…”

“…Although the HighG and LowNF variants of the LNA1 attain a higher gain than the LNAs reported in [2], [25], and [27], they consume a little more power (1.5-mW to 4.5-mW). However, the LNA1 LowP variant obtains a gain higher than the LNAs reported in [2], [25], and [27] with less power consumption (2-mW to 5-mW).…”

“…It provides excellent output-input isolation (reduced reverse transmission). While simultaneously attaining high gain, low NF, low current consumption, good input and output matching, and unconditional stability [1], [23]- [25]. Fig.…”

“…It has a series inductor (LINT) and a shunt capacitor (CINT) between the common-source (M1) and the common-gate (M2) transistors. In association with M1 and M2 capacitive parasitics, these elements form an artificial T-line allowing it to match the transistors' impedance to each other, improving the gain and noise figure [25]. Since the cascode of LNA3 is AC-coupled, this topology maintains the performance characteristics of the DC-coupled cascode, with the advantage that it works with lower voltage supplies.…”