Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology

Tripathi, Suman Lata; Patel, Govind Singh

doi:10.1007/s11277-019-06978-8

Cited by 20 publications

(3 citation statements)

References 22 publications

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“…Unit gain current cut-off frequency decreases; transit time also decreases with higher frequency f t values. τ will be less and it has led to greater switching speed of the device [29].…”

Section: Impact Of Transit Time(τ)mentioning

confidence: 99%

Performance optimization of AlGaAs and Al _x Ga _1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

Tamilarasi,

Karthik

2024

Phys. Scr.

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This work aims to enhance the effectiveness of the Double GateJunctionless Tunnel Field Effect Transistor (DG-JL-TFET) by optimizing the utilization of AlGaAs and GaAs/Si/AlGaAs-based Single Material and Tri-Materials(SM and TM). The TM structure demonstrates a greater On-State current (Ion)and a reduced Subthreshold Swing (SS) in comparison to SM- Structures. This study quantifies the two RF Performance Metrics, namely Unit-Gain-Current-Cut-off-Frequency (ft) and Maximum oscillation frequency fmax, by manipulating the structural factors such as gate length, gate oxide thickness, and Channel thickness. The TM structure exhibits a much greater On-State-Current (Ion) of 14 × 10−3mA compared to SM structures, while also reducing the Off-State-Current (Ioff ), Subthreshold Swing (SS) and Threshold-Voltage (Vt).TM structures exhibit higher values of ft and fmax in comparison to the SM structure of DG-JL-TFET due to their enhanced output conductance. Given the elevated magnitudes of (ft) and fmax, the device exhibits potential for forthcoming low-power-RF applications.

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“…Unit gain current cut-off frequency decreases; transit time also decreases with higher frequency f t values. τ will be less and it has led to greater switching speed of the device [29].…”

Section: Impact Of Transit Time(τ)mentioning

confidence: 99%

Performance optimization of AlGaAs and Al _x Ga _1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

Tamilarasi,

Karthik

2024

Phys. Scr.

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“…Though I ON is observed to be high, to improve I ON /I OFF , there are other factors such as effective mass (m*) of charge carriers that can be tuned 41 , 42 . I ON of poc-DG-AJLTFET is based on BTBT mechanism and critically depends on the transmission probability T WKB of the inter band tunneling barrier.…”

Section: Device Description and Simulationmentioning

confidence: 99%

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Boggarapu

Lakshmi

2023

Sci Rep

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This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

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“…The other devices like GAA-NWTFET, DGHG-FET, FinFET, Nanotube, TFET etc. [1][2][3][4][5][6][7][8] are recommended to minimize the SCEs and discover different way to examine lower off-current (I OFF ), power and reduced subthreshold-slope (SS) less than 60 mV/decade. From all the previous reported FETs based devices, TFET shows the required low SS and I OFF which is mostly preferred.…”

mentioning

confidence: 99%

Design and Analysis of Junctionless-Based Gate All Around N+ Doped Layer Nanowire TFET Biosensor

Kumar,

Raj,

Wadhwa

et al. 2024

ECS J. Solid State Sci. Technol.

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This work is based on the analysis and designing of gate all around N+-doped layer nanowire tunnel field-effect transistors (NTFET) without junctions for application in a biosensor by considering the various bio molecules like uricase, proteins, biotin, streptavidin, Aminopropyl-triethoxy-silane (ATS), and many more with dielectric modulation technique and gate-all-around (GAA) environment. Device sensitivity and tunneling probability is further improved by N+ doped layer (1×1020cm-3). The change in the subthreshold-slope (SS), drain current (ID), transconductance(gm), and ratio of ION/IOFF has been examined to detect the sensitivity of the proposed device by confining various biomolecules in the area of nanocavity. The nanocavity area creates a shield in the source gate of oxide layer and electrodes metal. The junctionless GAA-NTFET (JLGAA-NTFET) shows less leakage current and large control on the channel. The design of JLGAA-NTFET is with high doping concentration and observed higher sensitivity for APTS biomolecule which is suitable for sensor design application.

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Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology

Cited by 20 publications

References 22 publications

Performance optimization of AlGaAs and Al _x Ga _1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

Performance optimization of AlGaAs and Al _x Ga _1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Design and Analysis of Junctionless-Based Gate All Around N+ Doped Layer Nanowire TFET Biosensor

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Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology

Cited by 20 publications

References 22 publications

Performance optimization of AlGaAs and Al x Ga 1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

Performance optimization of AlGaAs and Al x Ga 1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Design and Analysis of Junctionless-Based Gate All Around N+ Doped Layer Nanowire TFET Biosensor

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Performance optimization of AlGaAs and Al _x Ga _1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

Performance optimization of AlGaAs and Al _x Ga _1−x As based SM-TM-DG-JL-TFET for an analog/RF applications