Design of Low power &amp;amp; Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding

Pande, Partha Pratim; Ganguly, Amlan; Feero, B.; Belzer, Benjamin J.; Grecu, C.

doi:10.1109/dft.2006.22

Cited by 46 publications

(36 citation statements)

References 15 publications

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“…The same approach is used in [14] to analyse the power of a new error recovery schemes for NoCs containing 5×5 crossbar switch. In addition, the energy overhead of using joint crosstalk avoidance and forward error correction coding is studied in [18]. The authors modelled every capacitance triggered due to use of the new method and then using them the dynamic energy overhead is calculated.…”

Section: Previous Workmentioning

confidence: 99%

A New Approach to Model the Effect of Topology on Testing Using Boundary Scan

et al. 2015

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In this paper, a new analytical approach is presented to study the effect of commonly used topologies on the energy consumption and delay of on chip network (NOC) testing using IEEE 1149.1 standard. Here, first we model the energy of each module in JTAG standard, and then using test access port (TAP) controller state diagram and test algorithm, the totoal energy based on each topology is calculated. In addition, the number of clocks is calculated and together with the propagation delay of basic gates, the test time is modelled and calculated. Using the results we can choose the least energyconsuming and fastet topology in terms of testing. The modelling is verified using FPGA implementation.

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Section: Previous Workmentioning

confidence: 99%

A New Approach to Model the Effect of Topology on Testing Using Boundary Scan

et al. 2015

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“…In another approach, Pande et al [25] propose to incorporate crosstalk avoidance coding and forward error correction schemes in the NoC data stream to enhance the system reliability.…”

Section: Link Testingmentioning

confidence: 99%

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Kakoee

Bertacco

Benini

2014

IEEE Trans. Comput.

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Abstract-In this work, we propose a distributed functional test mechanism for NoCs which scales to large-scale networks with general topologies and routing algorithms. Each router and its links are tested using neighbors in different phases. The router under test is in test mode while all other parts of the NoC are operational. We use triple module redundancy (TMR) for the robustness of all testing components that are added into the switch. Experimental results show that our functional test approach can detect stuck-at, short and delay faults in the routers and links. Our approach achieves 100 percent stuck-at fault coverage for the data path and 85 percent for the control paths including routing logic, FIFO's control path, and the arbiter of a 5 Â 5 router. We also show that our approach is able to detect delay faults in critical control and data paths. Synthesis results show that the area overhead of our test components with TMR support is 20 percent for covering stuck-at, delay, and short-wire faults and 7 percent for covering only stuck-at and delay faults in the 5 Â 5 router. Simulation results show that our online testing approach has an average latency overhead of 3 percent in PARSEC traffic benchmarks on an 8 Â 8 NoC.

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“…In another approach, Pande et al [13] propose to incorporate crosstalk avoidance coding and forward error correction schemes in the NoC data stream to enhance the system reliability.…”

Section: Related Workmentioning

confidence: 99%

“…Recent works have been addressing the test of the NoC infrastructure, including routers [8], [9], [10], [11] and interconnect channels [11], [12], [13]. Interconnect testing in NoC-based chips has been related to faults in wires within a single channel connecting two adjacent routers.…”

Section: Introductionmentioning

confidence: 99%