Design of high-throughput SHA-256 hash function based on FPGA

Suhaili, Shamsiah; Watanabe, Takahiro

doi:10.1109/iceei.2017.8312449

Cited by 27 publications

(9 citation statements)

References 5 publications

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“…The SHA-256 algorithm aims to produce a distinct digital fingerprint of a piece of data, such as a file or message. Creating a SHA-256 hash entails passing the input data through an advanced mathematical formula that yields a distinct output value [35]. This output value is the hash, a digital fingerprint of the input data.…”

Section: E the Cryptography Hash Function Sha-256mentioning

confidence: 99%

Securing Smart Grid Data With Blockchain and Wireless Sensor Networks: A Collaborative Approach

Almasabi,

Shaf,

Ali

et al. 2024

IEEE Access

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Section: E the Cryptography Hash Function Sha-256mentioning

confidence: 99%

Securing Smart Grid Data With Blockchain and Wireless Sensor Networks: A Collaborative Approach

Almasabi,

Shaf,

Ali

et al. 2024

IEEE Access

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“…The unfolding factor defines the number of iterations in the original program. This methodology is used to increase the performance of the SHA-256 design (Suhaili & Watanabe, 2017). The architecture is referred to as Register Transfer Level, and this strategy focuses on the latency of the designs (RTL).…”

Section: Introductionmentioning

confidence: 99%

FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation

Suhaili¹,

Julai²

2022

JST

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Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA-256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA-256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design.

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“…SHA-2 is crucial and advantageously used in a wide range of emerging applications such as cloud computing [2], security of reconfigurable computing platforms [3], blockchains [4][5][6], big data [7] and internet of things (IoTs) [1] [8] [9]. Therefore, several works focused on improving the performance (e.g., hashing speed, and power consumption) of SHA-2 on targeted devices such as graphics processing units (GPUs) [10] or field-programmable gate arrays (FPGAs) [11]. Acceleration of SHA-256 on FPGA has been the main focus of several previously published works, because of the inherent flexibility, performance, and reconfigurability architecture of FPGAs [12].…”

Section: Introductionmentioning

confidence: 99%

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL

Bensalem

Blaquiere

Savaria

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The Secure Hash Algorithm-256 (SHA-256) is a cryptographic function used in a wide variety of applications ranging from Internet of Things micro-devices to highperformance systems. This paper studies a set of implementations of the SHA-256 on a field-programmable gate array (FPGA) elaborated using the Open Computing Language (OpenCL). These implementations apply several optimization techniques to improve their respective throughputs. Reported results show that a combination of OpenCL optimization techniques allows obtaining an implementation offering a 90x speed-up when compared to an unoptimized OpenCL implementation. Moreover, the best reported optimized implementation achieves a throughput of 3973 Mbps, which is 4.3 times higher than the best previously published HLS-based SHA-256 implementation and even higher than the previously published implementations using a hardware description language. To our knowledge, this work is the first that proposes an OpenCL-based FPGA implementation of SHA-256 and its OpenCL-based optimization methodology.

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Design of high-throughput SHA-256 hash function based on FPGA

Cited by 27 publications

References 5 publications

Securing Smart Grid Data With Blockchain and Wireless Sensor Networks: A Collaborative Approach

Securing Smart Grid Data With Blockchain and Wireless Sensor Networks: A Collaborative Approach

FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL

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