Design of efficient on-chip communication architecture in MpSoC

Shanthi, D.; Amutha, R.

doi:10.1109/icrtit.2011.5972368

Cited by 13 publications

(4 citation statements)

References 14 publications

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“…Fig.4 shows that the proposed synchronous-toasynchronous packaging module can accomplish the conversion of the four-input synchronous signals. When the converted signal is received by asynchronous module, it will be Null state according to four-phase protocol to prepare for next work [9,10]. It can be seen from Fig.5 that, the two signals produced by asynchronous arbiter is converted to synchronous signal of binary encoding which can be read by synchronous module through the asynchronous-to-synchronous packaging circuit.…”

Section: Simulations and Analyses Of Resultsmentioning

confidence: 99%

A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under four-phase dual-rail protocol

Yang

Zhang

2013

2013 14th International Conference on Electronic Packaging Technology

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Asynchronous circuits have the advantages of high speed and low power consumption, but they can not work together with the synchronous module, thus synchronous and asynchronous packaging circuits become the research focus in GALS(globally asynchronous locally synchronous) bus systems. In this paper, a synchronous and asynchronous packaging circuit of asynchronous arbiters under four-phase dual-rail protocol is designed based on the standard gates. Verifications of the packaging circuit are implemented on Xilinx Viretex5 of 65nm CMOS technology. The results show that the power decreased by 88.3%, the working speed of synchronous-to-asynchronous module increased by 55.4%, and the working speed of asynchronous-to-synchronous module increased by 61.4% compared with the traditional suspended clock packaging circuits.

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Section: Simulations and Analyses Of Resultsmentioning

confidence: 99%

A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under four-phase dual-rail protocol

Yang

Zhang

2013

2013 14th International Conference on Electronic Packaging Technology

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“…Adaptive Arbiter (AA) used by Haishan Li et al [14] is better than the conventional arbiters in terms of fair bandwidth allotment and latency. Since arbiter is an important functional module in multiprocessor, therefore it should be carefully designed in high performance systems [17]. In order to optimize the performance of the bus, the time required to handle the request should be minimized [18,19].…”

Section: Cmentioning

confidence: 99%

An intelligent arbiter for maximum CPU utilization, fair bandwidth allocation and low latency: Survey

Akhtar

Sidek

2012

2012 IEEE 8th International Colloquium on Signal Processing and Its Applications

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Accelerated advancement in the world of microprocessor necessitates solving the bus contention in a most efficient manner. The major challenge is to reduce the latency of the system and to achieve a fair bandwidth allocation using maximum CPU utilization. Combination of Adaptive Arbitration algorithm and the processors according to their traffic behavior can be one of the feasible options to tackle the aforesaid problems due to its fair bandwidth allotment and low system latency. This article provides a comprehensive picture of research and developments in dynamic arbitration algorithm for masters according to the traffic behavior. The papers published in standard journals are reviewed, classified according to their objectives and presented with a general conclusion. Keywords-adaptive arbiter; fair bandwidth; low latency; system-onchip; traffic behaviorI.978-1-4673-0961-5/12/$31.00 ©2012 IEEE

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“…A dynamic round robin arbiter based on lottery method using VHDL is implemented in [8]. The results of the implemented model, which are shown on ModelSim tool, show that the latency is improved with the dynamic tickets more than the static tickets and the starvation is avoided.…”

Section: Related Workmentioning

confidence: 99%

A Bus Arbitration Scheme with an Efficient Utilization and Distribution

El-Kustaban¹,

Qahtan²

2017

ijacsa

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Abstract-Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to place several processors on the same chip die to get Chip Multiprocessor (CMP). The shared bus is the most common media used to connect these processors with each other and with the shared resources. Distributing the shared bus among the contention processors represents a critical issue that affects overall performance of the CMP. Optimal utilization with fair distribution of the shared bus represents another challenge. This paper introduces a bus arbitration scheme, which is an AgeBased Lottery (ABL) Arbitration that combines the lottery and age-based algorithms to overcome the shared bus challenges. The results show that the developed bus arbitration scheme maximizes the bus utilization and improves the distribution by at least 13.5% with an acceptable latency time comparing to the traditional bus arbitration schemes.

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Design of efficient on-chip communication architecture in MpSoC

Cited by 13 publications

References 14 publications

A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under four-phase dual-rail protocol

A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under four-phase dual-rail protocol

An intelligent arbiter for maximum CPU utilization, fair bandwidth allocation and low latency: Survey

A Bus Arbitration Scheme with an Efficient Utilization and Distribution

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