A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under four-phase dual-rail protocol

Abstract

Asynchronous circuits have the advantages of high speed and low power consumption, but they can not work together with the synchronous module, thus synchronous and asynchronous packaging circuits become the research focus in GALS(globally asynchronous locally synchronous) bus systems. In this paper, a synchronous and asynchronous packaging circuit of asynchronous arbiters under four-phase dual-rail protocol is designed based on the standard gates. Verifications of the packaging circuit are implemented on Xilinx Viretex5 of 65nm CMOS technology. The results show that the power decreased by 88.3%, the working speed of synchronous-to-asynchronous module increased by 55.4%, and the working speed of asynchronous-to-synchronous module increased by 61.4% compared with the traditional suspended clock packaging circuits.