An intelligent arbiter for maximum CPU utilization, fair bandwidth allocation and low latency: Survey

Abstract

Accelerated advancement in the world of microprocessor necessitates solving the bus contention in a most efficient manner. The major challenge is to reduce the latency of the system and to achieve a fair bandwidth allocation using maximum CPU utilization. Combination of Adaptive Arbitration algorithm and the processors according to their traffic behavior can be one of the feasible options to tackle the aforesaid problems due to its fair bandwidth allotment and low system latency. This article provides a comprehensive picture of research and developments in dynamic arbitration algorithm for masters according to the traffic behavior. The papers published in standard journals are reviewed, classified according to their objectives and presented with a general conclusion. Keywords-adaptive arbiter; fair bandwidth; low latency; system-onchip; traffic behaviorI.978-1-4673-0961-5/12/$31.00 ©2012 IEEE