We present a high-performance bilayer graphene (BLG) and mercury cadmium telluride (Hg1−xCdx=0.1867Te) heterojunction based very long wavelength infrared (VLWIR) conductive photodetector.
This paper presents three self-powered photodetectors namely, p+-bilayer graphene (BLG)/n+-ZnO nanowires (NWs), p+-BLG/n+-Si NWs/p–-Si and p+-BLG/n+-ZnO NWs/p–-Si. The Silvaco Atlas TCAD software is utilized to characterize the optoelectronic properties of all the devices and is validated by analytical modeling. The proposed dual-junction photodetectors cover broadband spectral response varying from ultraviolet to near-infrared wavelengths. The dual-heterojunction broadband photodetector exhibits photocurrent switching with the rise and fall time of 1.48 and 1.27 ns, respectively. At −0.5 V bias, the highest external quantum efficiency, photocurrent responsivity, specific detectivity, and the lowest noise equivalent power of 71%, 0.28 A W−1, 4.2 × 1012 cmHz1/2 W−1, and 2.59 × 10–17 W, respectively, are found for the dual-heterojunction device with a wavelength of 480 nm at 300 K. The proposed nanowires based photodetectors offer great potential to be utilized as next-generation optoelectronic devices.
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. [5]. Locking time, lock range and jitter performance, static phase error, low power consumption and immunity against process voltage temperature loading (PVTL) variations are the most important metrics of a DLL. A DLL can be realized by a number of architectures; analog and digital DLLs are the two most important types among them [6]. Analog DLLs have better performance in terms of jitter, layout area, power supply rejection ratio, power consumption and clock skew. This paper introduces a mixed mode DLL in which single ended differential pair based VCDL is used which provides high stability against temperature and power supply variations. The proposed circuit depicts superior performance in terms of speed, power consumption, and locking range. The organization of remaning four sections are starting with architecture of basic DLL followed by analysis of different blocks, simulation results and conclusion.
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