Design of defect tolerant tile-based QCA circuits

Abstract

In this paper, a novel CAD-based approach is presented for defect tolerance of QCA circuits. This approach is based on using QCA tiles and provides defect tolerance at circuit level with, in most cases, no area overhead. A ranking methodology is introduced to determine the tile configurations and logic functions that are optimal for logic synthesis of QCA circuits. Simulations on benchmark circuits show that the proposed methodology provides significant improvements in defect tolerance compared with QCA gate-based designs.

Self organization on a swarm computing fabric

“…The continuous scaling of the CMOS technology makes progressively harder to exhaustively test the functionality of a chip to determine the absence of design errors, and all the more so for the defects that could arise during the production phases. At the same time, emerging technologies require complex nanoscale processes, such as bottom-up self assembly, used to replace traditional VLSI lithography, characterized by higher defect density compared to VLSI [22]. Without any specific strategies, generally speaking, a single fault could cause the fault of the whole system.…”