Design of Cryptographic Devices Resilient to Fault Injection Attacks Using Nonlinear Robust Codes

Akdemir, Kahraman D.; Wang, Zhen; Karpovsky, Mark G.; Sunar, Berk

doi:10.1007/978-3-642-29656-7_11

Cited by 16 publications

(12 citation statements)

References 29 publications

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“…0.25 and 0.00625 for the nonlinear code over GF (2), GF(4) and GF (16), respectively). The deviations of the measured ASR from these values are much larger for the Braun multiplier.…”

Section: B Evaluation Of Hardening For Single Faultsmentioning

confidence: 99%

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Cross-level protection of circuits against faults and malicious attacks

Tomashevich

Srinivasan

Foerg

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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Nanoscale electronics is increasingly affected by disturbances caused by radiation, noise and effects of statistical process variations. Moreover, deliberate injection of faults into cryptographic circuits is used by malicious attackers to perform cryptanalysis and gain access to sensitive information. Error-detecting codes are employed to protect circuits against such disturbances, and new advanced codes specifically designed to counter malicious attacks have recently been introduced. However, a number of logic gates in the circuit are not adequately protected by the error-detecting code, as faults affecting these gates escape detection with a relatively high probability. We introduce a cross-level protection solution, where a light-weight error-detecting code is combined with hardening of insufficiently protected gates using transistor resizing. Such gates are determined by FPGA-supported fault injection. A thorough electrical analysis is performed in order to modify the electrical parameters of these gates such that faults are highly unlikely. We report area and power overhead for a number of error-detecting codes. To the best of our knowledge, this is the first work which co-optimizes fault handling by information redundancy based on error-detecting codes and by hardening individual circuit elements.

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“…0.25 and 0.00625 for the nonlinear code over GF (2), GF(4) and GF (16), respectively). The deviations of the measured ASR from these values are much larger for the Braun multiplier.…”

Section: B Evaluation Of Hardening For Single Faultsmentioning

confidence: 99%

“…We used exhaustive simulation of all 256 possible input vectors for the Braun multiplier and 1,000 random vectors for b20. We synthesized four EDC-based protection architectures for these circuits using linear parity and nonlinear parity codes over GF (2), GF(4) and GF (16). These codes employ 1, 1, 2 and 4 checkbits, respectively.…”

Section: A Unhardened Circuitmentioning

confidence: 99%

Cross-level protection of circuits against faults and malicious attacks

Tomashevich

Srinivasan

Foerg

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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“…As an illustrative example, the design of secure multipliers (widely used as sub-blocks in public-key cryptosystems) based on multilinear arithmetic codes will be shown. As in most papers on protecting the data path of cryptographic devices, e.g., see [11]- [13], we assume that countermeasures are implemented in the cryptographic device preventing the attackers from tampering with the clock signals. We further assume that a low-rate true random number generator (e.g., [14]) is available.…”

Section: Introductionmentioning

confidence: 99%

Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes

Wang

Karpovsky

Joshi

2012

IEEE Trans. VLSI Syst.

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Public-key cryptographic devices are vulnerable to fault-injection attacks. As countermeasures, a number of secure architectures based on linear and nonlinear error detecting codes were proposed. Linear codes provide protection only against primitive adversaries with limited attack capabilities. On the other hand nonlinear codes provide protection against strong adversaries, but at the price of high area overhead (200%-400%). In this paper we propose a novel error detection technique based on the random selection of linear arithmetic codes and explore the use of this technique for the protection of the multiplier, which is a basic block in many public-key cryptographic devices. The error detection technique does not imply any limitations on the types of errors at the output of the device, e.g., the multiplicity of the error does not have to be small. Under mild assumptions the proposed construction achieves near nonlinear code error detection performance at a lower cost (at most 50% area overhead for the protection of multipliers) due to the fact that no nonlinear operations are needed for the encoder and decoder.

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“…The first requirement can be achieved by implementing the reconfiguration function using a fault injection aware design at a reasonable performance penalty [38,1]. Moreover, although fault injection attacks against non-volatile memory (e.g., EEPROM or Flash) are known [51], it seems to be difficult in practice to perform invasive attacks that change the content of specific non-volatile memory cells without affecting the content of the surrounding cells [52].…”

Section: Requirementsmentioning

confidence: 99%

“…Therefore, only the error correction mechanism must be implemented when building an LR-PUF based on a controlled PUF. Moreover, the non-volatile memory and control logic should be protected against fault-injection attacks, e.g., by applying the techniques described in [38,1].…”

Section: Implementation and Performance Evaluationmentioning

confidence: 99%

Recyclable PUFs: logically reconfigurable PUFs

et al. 2011

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Abstract. Physically Unclonable Functions (PUFs) are security primitives that exploit intrinsic random physical variations of hardware components. In the recent years, many security solutions based on PUFs have been proposed, including identification/authentication schemes, key storage and hardware-entangled cryptography. Existing PUF instantiations typically exhibit a static challenge/response behavior, while many practical applications would benefit from reconfigurable PUFs. Examples include the revocation or update of "secrets" in PUF-based key storage or cryptographic primitives based on PUFs. In this paper, we present the concept of Logically Reconfigurable PUFs (LR-PUFs) that allow changing the challenge/response behavior without physically replacing or modifying the underlying PUF. We present two efficient LR-PUF constructions and evaluate their performance and security. In this context, we introduce a formal security model for LR-PUFs. Finally, we discuss several practical applications of LR-PUFs focusing on lightweight solutions for resource-constrained embedded devices, in particular RFIDs.

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Design of Cryptographic Devices Resilient to Fault Injection Attacks Using Nonlinear Robust Codes

Cited by 16 publications

References 29 publications

Cross-level protection of circuits against faults and malicious attacks

Cross-level protection of circuits against faults and malicious attacks

Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes

Recyclable PUFs: logically reconfigurable PUFs

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