Design of asynchronous SAR ADC for low power mixed signal applications

Verma, Deeksha; Kang, Hye Yeong; Shehzad, Khuram; Rehman, Muhammad Riaz Ur; Lee, Kang-Yoon

doi:10.1109/isocc.2017.8368863

Cited by 6 publications

(6 citation statements)

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“…The proposed ADC is similar to an asynchronous SAR ADC [6,7,8,9,10,11,12], a pipelined ADC [1], a subranging ADC [1], or a binary-search ADC [28,29,30,31] in some aspects, but has several different points.…”

Section: Discussionmentioning

confidence: 99%

“…The ADC is a key circuit for interface between analog and digital worlds [1,2,3]. Much attention has been paid to the SAR ADC due to small chip area and low power as well as no need for operational amplifier [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18], and its figure of merits (FOM) has been improved. The Hopfield network has been investigated as an ADC architecture for several tens of years [19,20,21,22,23,24], but it has not been widely used in practice.…”

Section: Introductionmentioning

confidence: 99%

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Asynchronous capacitive SAR ADC based on Hopfield network

Bai

Katayama

Yao

et al. 2022

IEICE Electron. Express

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This letter revisits a Hopfield network for an SAR ADC configuration, which enables low voltage, low power and fast operation with small circuitry. It employs an asymmetrical Hopfield network to avoid local minimum, and it uses capacitors and switches instead of very large resistors. Our N-bit SAR ADC uses N chopper-type comparators with asynchronous parallel operation, which is different from the conventional asynchronous SAR ADC employing only one comparator. It requires only the sampling clock for each input data sampling; no internal high frequency clock is required. Its AD conversion time is determined only by the comparator delays and the capacitor charge/discharge settling times; hence it is very fast and the AD conversion latency is only one or two clock cycles. Its operation is verified with SPICE simulations.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Asynchronous capacitive SAR ADC based on Hopfield network

Bai

Katayama

Yao

et al. 2022

IEICE Electron. Express

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“…A linear link among the digital input code and analog output voltage is provided by this architecture, allowing for precise voltage representation. The R-2R DAC design has benefits such as a lower component count, better linearity, and simplicity in calibration [14]. The R-2R DAC transforms the digital output code from the SAR logic into a precise analog voltage signal in the 16-bit SAR ADC.…”

Section: Design Of Sar Adcmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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“…For low-power applications, a Successive Approximation Register (SAR) analog-to-digital converter (ADC) is a good choice to obtain successive digital code from an analog input by using the binary search algorithm. Due to its simplicity and power efficiency, SAR ADC is more popular and favorable for comparison with other types of ADCs [ 1 , 2 , 3 ]. Traditionally, pipeline ADCs have been frequently used for high-speed and medium-resolution data converters.…”

Section: Introductionmentioning

confidence: 99%

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

Verma

Shehzad

Kim

et al. 2022

Sensors

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A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

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Design of asynchronous SAR ADC for low power mixed signal applications

Cited by 6 publications

References 1 publication

Asynchronous capacitive SAR ADC based on Hopfield network

Asynchronous capacitive SAR ADC based on Hopfield network

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

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Design of asynchronous SAR ADC for low power mixed signal applications

Cited by 6 publications

References 1 publication

Asynchronous capacitive SAR ADC based on Hopfield network

Asynchronous capacitive SAR ADC based on Hopfield network

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

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Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications