Design of a digital FM demodulator based on a 2nd° order all-digital phase-locked loop

Abstract

A software-defined radio (SDR) is a wireless communication device in which all of the signal processing is implemented in software. By simply downloading a new program, a SDR is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, FPGAs have been used extensively for implementing essential functions in SDR architectures. In this paper, we explore the design of a Digital FM Receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The digital FM Receiver circuit is designed using pure VHDL, then simulated and synthesized using ModelSim SE 6 and LeonardoSpectrum Level 3, respectively. The final circuit operates at a frequency up to 150MHz and occupies the area around 15K logic gates.

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

“…Another FM receiver circuit has also been designed and synthesized using the Leonardo Spectrum 2004a.63 from Mentor Graphics and TSMC 350 nm (Fast) as a target technology library. From Tables 7 and 8, it is observed that the FM demodulator designed in this chapter is better in performance compared to the available DPLL-based FM demodulator [5,6].…”

“…There exist various architectures [5][6][7][8][9][10][11][12][13][14] for implementing digital FM demodulator into a single chip, although their performance has mostly been limited by analog signal processing accuracy. The basic fundamentals behind FM demodulation are how to discriminate accurately a small 2 International Journal of Reconfigurable Computing frequency deviation of the FM-modulated signal from its center frequency.…”

“…An alternative solution is to implement it in FPGA due to its flexibility and modularity. A reduced-area, low-power, and high-speed linear digital FM demodulator using the DPLL technique [5,6] has been implemented towards the development of an SDR system. Componentwise improvements have been carried out in this work to get compact architecture, a faster system clock, and achieve a less power consumption while compared with existing implementations of digital FM demodulator.…”

“…Timing analysis comparison with other FM demodulator implementation[5,6]. MHz Operating frequency 143.7 MHz Operating frequency 158.1 MHz Operating frequency 155.8 MHz the designed circuit can effectively demodulate the FM input signal back to its original form.…”

ALL Digital Phase-Locked Loop (ADPLL): A Survey

“…In 2005's, a frequency modulated receiving system based on ADPLL was proposed [2] .In 2006's double edge triggered D flip-flop as phase detector was proposed [3] This design reduced 33% of power dissipation. In 2008's digital fm demodulator was proposed [4] It was designed by VHDL. In 2009's frequency modulated modem was implemented on field programmable array (FPGA) [5] In 2010's a field programmable array based linear ADPLL was proposed.…”