Design of a 3.3-V 1.2-GHz pipelined multiplier to implement energy-efficient multimedia applications

Aguirre, Mariano; Salim, Mustafa; Linares, M.

doi:10.1109/mwscas.2005.1594373

Cited by 2 publications

(4 citation statements)

References 5 publications

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“…The detailed comparison on critical parameters with other competitive designs is avoided here for the sake of brevity. However, a benchmarking exercise only on speed and power dissipation, with ten recent competitive designs, namely of [1, 3–9, 16, 24] show that the proposed work outperforms all the others. This is because of modified architecture combined with effective wave‐pipelining with pair‐wise multiplication algorithm.…”

Section: Discussionmentioning

confidence: 97%

“…Each partial product however is represented by summation of two numbers corresponding to even and odd terms [1]. Thus P ee = even P ee + odd P ee (4) P eo = even P eo + odd P eo (5) P oe = even P oe + odd P oe (6)…”

Section: Pair-wise Algorithmmentioning

confidence: 99%

“…Multiplication is one of the critical operations in all computation intensive applications [1][2][3][4][5][6][7][8][9]. Low-power consumption is a criterion for many battery operated systems.…”

Section: Introductionmentioning

confidence: 99%

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Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

Saha¹,

Pal

Chandra

2013

IET Circuits, Devices & Systems

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In this study, a low-power, high-speed, layout-efficient 8b ×8b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 µm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.

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Section: Discussionmentioning

confidence: 97%

Section: Pair-wise Algorithmmentioning

confidence: 99%

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Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

Saha¹,

Pal

Chandra

2013

IET Circuits, Devices & Systems

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“…Several low-power and high-performance 1-bit hybrid Full Adder cells have been reported in the literature [2][3][4][5][6][7][8][9][10][11][12][13]. In this work four state-of-the-art hybrid Full Adder Cells ( Fig.…”

Section: Hybrid Adder Cellsmentioning

confidence: 99%

Hybrid adders for high-speed arithmetic circuits: A comparison

Aranda

Báez

Díaz

2010

2010 7th International Conference on Electrical Engineering Computing Science and Automatic Control

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In this paper the most interesting topologies of one-bit hybrid full adders, are analyzed and compared for speed, power consumption, and power-delay product. The investigation has been carried out with properly defined simulation set up and input pattern on a Mentor Graphics environment using a TSMC 180 nm CMOS process. Performance has been also compared for different supply voltage values. The simulation results show that the Chang adder is the best in terms of PDP figure of merit; however the Aguirre adder is the best in terms of driving capability even at low power supply.

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Design of a 3.3-V 1.2-GHz pipelined multiplier to implement energy-efficient multimedia applications

Cited by 2 publications

References 5 publications

Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

Hybrid adders for high-speed arithmetic circuits: A comparison

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