Design of 0.35-mm pitch QFP lead and its assembly technology

Totani, Masayasu; Teshima, Yasuhiro; Ito, Nobuyasu; Nagatake, Mami; Otaguro, Harumi

doi:10.1109/96.404103

Cited by 3 publications

(1 citation statement)

References 32 publications

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“…It is also easy to be tested and reworked as all the leads and their solder joints are visible. Thus, defects or failure of this package in some complicated dense packaging electronic products could be observed and fixed conveniently and efficiently [4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Performance of a hybrid fine pitch quad flat package mounted with a new flux on printed circuit board in surface insulation resistance test

Zhou

Haseeb

Andriyana

et al. 2020

Materialwissenschaft Werkst

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An innovative hybrid quad flat package is designed recently by incorporating two types of leads with two distinctive shapes: gull wing and J-lead. These leads are separated into two layers to increase the adjacent space between them. Pure tin is used as the connector finish in the package, while Sn-3.0 Ag-0.5Cu solder material with a new flux is printed on the footprint copper pads of printed circuit board to join the hybrid packages on it. As compared to the conventional quad flat package, the design significantly increases the lead count by 50 % and reduces the distance between two types of leads to 0.325 mm, consequently improving the functional capability in a smaller size product. Surface insulation resistance test is conducted according to IPC-TM-650 standard to analyse the reliability of the newly designed hybrid quad flat package. The absence of tin whisker and dendrite after the test demonstrates the reliability of this hybrid package product and the new flux applied. Keywords: Reliability / scanning electron microscope / hybrid / flux / quad flat package Eine innovative, rechteckige hybride Flachbaugruppe, die zwei unterschiedliche Pintypen, gull wing und J-Lead, kombiniert, wurde entworfen. Diese Pins sind über zwei Schichten verteilt, damit der Pinabstand vergrößert wird. Auf der Oberfläche des Steckverbinders wird reines Zinn verwendet. Auf den Kupferpads der Leiterplatte wurde ein Sn-3.0 Ag-0.5Cu-Lot mit einem neuen Flussmittel benutzt, um die gemischten Pakete zu verbinden. Dieses Design erhöht die Anzahl der Pins um 50 %, im Vergleich zu einer herkömmlichen, rechteckigen Flachbaugruppe, weil der Pinabstand auf 0,325 mm reduziert wird. Dies verbessert somit die Funktionsfähigkeit eines kleineren Produkts. Der Oberflächenisolationswiderstand ist dem IPC-TM-650-Standard gemäß getestet, um die Zuverlässigkeit der neuen Flach

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Section: Introductionmentioning

confidence: 99%

Performance of a hybrid fine pitch quad flat package mounted with a new flux on printed circuit board in surface insulation resistance test

Zhou

Haseeb

Andriyana

et al. 2020

Materialwissenschaft Werkst

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Numerical analysis on the influent factors of the interface stress of 63Sn37Pb under the temperature cycle condition

Jin

et al. 2009

2009 8th International Conference on Reliability, Maintainability and Safety

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3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

Lee

Liu²,

Chiang³

2007

IEEE Trans. Comp. Packag. Technol.

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With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) [1] with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design.Index Terms-Bubble-like stress buffer layer, chip scale packages (CSP), finite element method (FEM), reliability, simulation, wafer level packages (WLP).

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Design of 0.35-mm pitch QFP lead and its assembly technology

Cited by 3 publications

References 32 publications

Performance of a hybrid fine pitch quad flat package mounted with a new flux on printed circuit board in surface insulation resistance test

Performance of a hybrid fine pitch quad flat package mounted with a new flux on printed circuit board in surface insulation resistance test

Numerical analysis on the influent factors of the interface stress of 63Sn37Pb under the temperature cycle condition

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

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