Design for testability of mixed signal integrated circuits

Wagner, K.D.; Williams, T.W.

doi:10.1109/test.1988.207869

Cited by 84 publications

(20 citation statements)

References 6 publications

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“…In the long run, this approach has implications on DFT [23], [24]. A hierarchical approach to testing is suggested in order to keep the simulation requirements and the ANN size reasonable.…”

Section: Discussionmentioning

confidence: 99%

Linear circuit fault diagnosis using neuromorphic analyzers

Spina

Upadhyaya

1997

IEEE Trans. Circuits Syst. II

159

102

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This paper presents a method of analog fault diagnosis using neural networks. The primary focus of the paper is to provide robust diagnosis using a simple mechanism for automatic test pattern generation while reducing test time. A new diagnosis framework consisting of a white noise generator and an artificial neural network for response analysis and classification is proposed. This approach moves the diagnosis of analog circuits closer to the goal of built-in test. Networks of reasonable dimension are shown to be capable of robust diagnosis of analog circuits including effects due to tolerances.

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Section: Discussionmentioning

confidence: 99%

Linear circuit fault diagnosis using neuromorphic analyzers

Spina

Upadhyaya

1997

IEEE Trans. Circuits Syst. II

159

102

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“…In order to overcome the problem of the limited accessibility in ICs, design for testability measures have to be taken to improve the controllability and observability by propagating test signals from the external IC pins to and from internal, otherwise inaccessible nodes [140]. These measures can for instance take the form of extra test pins or extra test structures [e.g., (de)multiplexers] to isolate and individually test the different analog blocks in the system [144], analog scan path techniques to read out selected test node signals into a serial scan path [145], or extra circuitry to reconfigure the circuit in the test mode, e.g., use a feedback structure to reconfigure the circuit into an oscillator mode where the oscillation frequency then indicates whether the circuit is faulty or fault-free [146].…”

Section: F Analog and Mixed-signal Testing And Design For Testabilitymentioning

confidence: 99%

Computer-aided design of analog and mixed-signal integrated circuits

2000

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“…A number of approaches have been proposed including signal multiplexing [5], analogue test tables [6], analogue scan path [7] and hybrid built-in self test (HBIST) [8]. Whilst such methods can be used to test the individual partitions, the correct operation of the combined units can not be guaranteed.…”

Section: Introductionmentioning

confidence: 99%

Built-in self test of S2I switched current circuits

Saether¹,

Toumazou²,

Taylor

et al. 1996

Analog Integr Circ Sig Process

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This article presents a new concept for built-in self test of switched current circuits based on $2I memory cells. From the spectrum of possible transistor defects reported in CMOS processes [1] [2], five different faultsituations were modelled and the ability to detect the various failures was studied. This was accomplished by simulating a simple switched-current integrator in which all the different failures were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be readily realised with a minimum of additional overhead circuitry.

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Design for testability of mixed signal integrated circuits

Cited by 84 publications

References 6 publications

Linear circuit fault diagnosis using neuromorphic analyzers

Linear circuit fault diagnosis using neuromorphic analyzers

Computer-aided design of analog and mixed-signal integrated circuits

Built-in self test of S2I switched current circuits

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