Built-in self test of S2I switched current circuits

Abstract

This article presents a new concept for built-in self test of switched current circuits based on $2I memory cells. From the spectrum of possible transistor defects reported in CMOS processes [1] [2], five different faultsituations were modelled and the ability to detect the various failures was studied. This was accomplished by simulating a simple switched-current integrator in which all the different failures were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be readily realised with a minimum of additional overhead circuitry.

Implicit functional testing of switched current filter based on fault signatures

“…However, concerning the testing aspect, the test techniques proposed for analog circuits are not readily applicable to SI circuits. The few papers dedicated to the test of SI circuits principally concern test methodology, test generation, DFT, and BIST [1][2][3][4]. Recently, the concept of implicit functional testing was introduced in [5][6][7][8], these works used pseudorandom approach transferred digital test technology to the analog test, for detection and localization of parametric faults in analog circuits by evaluating different circuit responses.…”

A Study of Kurtosis-Based Dictionary-Diagnosis Method against Switch-Current Circuit Faults

“…These publications include the testing method of oscillation abilities of switch-current-biquadratic-filter proposed by G. E. Taylor et al [3,4] ; the reforming method of a two-circuit structure into a cascade-current-mirror structure by changing the clock, and the comparing method of DC input and output signals by Saether et al [5] ; and the BIST method by M.Renovell [6] suitable for using the same switch-current storage-unit circuit.…”

BIST design for analog cell matching

“…The information is distributed along the network structure, often with redundancy, and requires less typical methods to cover fault detections in an effective manner [2]. Hence, existent BIST techniques applied to basic building circuits, such as switched-current (SI) memories [3]- [5], capacitor arrays [6], and analog filters [7], can be inefficient as a test procedure for analog computational networks. Global methods are required for parametric-faults detection, which should focus on system performance rather than component level, and make adjustments accordingly.…”