This article presents a new concept for CO current self test of switched current circuits based on S I cells as basic building blocks. Six different transistor faults were modelled and the ability to detect the various faultsituations was studied. The fault detection system presented was applied to a simple switched-current integrator in which all the different faults were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be realised with a minimum of additional overhead circuitry.
This article presents a new concept for built-in self test of switched current circuits based on $2I memory cells. From the spectrum of possible transistor defects reported in CMOS processes [1] [2], five different faultsituations were modelled and the ability to detect the various failures was studied. This was accomplished by simulating a simple switched-current integrator in which all the different failures were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be readily realised with a minimum of additional overhead circuitry.
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