This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.
This paper presents an initiative to involve ECE undergraduate students in the design and deployment of a network infrastructure for an academic laboratory. The project aims at attaining a reliable and secure network for an IC CAD environment. The students focused on employing secure authentication, accounting and storage with single sign-on, based on enterprise-grade, open-source protocols. This initiative proved to be highly motivating and allowed the students to develop knowledge and hands-on experience on the area of network security. The resulting network design and core infrastructure is herein described as well as its deployment in a real microelectronics design environment.
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