Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits

Abstract

Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. The same security assessment method is then applied to a built-in-self-test (BIST) structure where it is shown that even BIST structures can cause security vulnerabilities. To balance trustworthiness and testability, a new design-for-security (DFS) methodology is proposed which, through the modification of scan chain structure, can achieve high security without compromising the testability of the inserted scan structure. To support the task of secure scan chain insertion, a method of scan chain reshuffling is introduced. Using an AES encryption core as the testing platform, we elaborated the security assessment procedure as well as the DFS technique in balancing security and testability of cryptographic circuits.

Pre-silicon security verification and validation

“…Besides the RTL code verification, the proof-carrying based information assurance scheme was extended to support gate level circuit netlist [18]. By leveraging the new gate-level framework, the authors in [18] formally analyzed the security of design-for-test (DFT) scan chains, the industrial standard testing method, and formally proved that a circuit with scan chain can violate data secrecy property.…”

“…By leveraging the new gate-level framework, the authors in [18] formally analyzed the security of design-for-test (DFT) scan chains, the industrial standard testing method, and formally proved that a circuit with scan chain can violate data secrecy property. Although security concerns caused by DFT scan chains have been under investigation for decades, with various attack and defense methods being developed [8,29,33,34,37,38], it is the first time it has been formally proved that the scan chain inserted designs are vulnerable (Note that RTL verification methods can rarely touch scan chains because scan chains are inserted in the netlist).…”

“…Although security concerns caused by DFT scan chains have been under investigation for decades, with various attack and defense methods being developed [8,29,33,34,37,38], it is the first time it has been formally proved that the scan chain inserted designs are vulnerable (Note that RTL verification methods can rarely touch scan chains because scan chains are inserted in the netlist). The same framework was also applied in built-in-self-test (BIST) structure to prove that BIST structure can also leak internal sensitive information [18].…”

“…Although at its early stage, formal methods have already shown their benefits over testing methods in exhaustive security verification [18,21,25,39]. A multi-stage approach, which included assertion based verification, code coverage analysis, redundant circuit removal, equivalence analysis, and use of sequential Automatic Test Pattern Generation (ATPG) was adopted in [39] to identify suspicious signals for detecting Hardware Trojans.…”

“…This approach was demonstrated on a RS232 circuit and the efficiency of the approach in detecting Trojan signals ranged between 67.7% and 100%. In [18,21,25], the PCH framework was used to verify security properties on soft IP cores. Supported by the Coq proof assistant [17], formal security properties can be formalized and proved to ensure the trustworthiness of IP cores.…”