Vulnerability modelling of crypto‐chips against scan‐based attacks

Scan‐based attack tolerance with minimum testability loss: a gate‐level approach

“…To protect a scan-enabled chip against scan-based attacks, we should consider the fact that different parts of the chip have different contributions in a successful scan-based attack. Vulnerability modelling [26] of a crypto-chip against scan-based attacks revealed that not all parts of a chip have the same contribution in a successful scan-based attack. To have an efficient attack tolerance mechanism, we need to consider this fact.…”

“…To have an efficient attack tolerance mechanism, we need to consider this fact. For example, a gate-level vulnerability model proposed in [26] is based on the fact that preventing the first step of a structural scan-based attack, i.e. extracting the input to scan cell(s) mapping, would save the ground of the crypto-chip against structural scan-based attacks.…”

“…We have used the vulnerability model proposed in [26] to achieve the most efficient scan-based attack tolerance with the lowest testability loss in this study. Our proposed methods are discussed in the next section.…”

“…We propose a set of gate-level protection mechanisms to be used by IP designers to make crypto-chip immune against scan-based attacks. The proposed method uses our previously proposed vulnerability model [26] to find a set of most vulnerable nets in the gate-level netlist of a crypto-chip. The set of determined nets are then pruned using a proposed method in this study and then are protected using gate and register transfer level (RT level) protection methods with an almost no testability loss.…”

“…• A net pruning method is proposed to compress the set of scanbased attack vulnerable nets. Such nets are extracted from the gate-level netlist of the crypto-chip using the vulnerability model proposed in [26]. • Gate and RT level methods for net masking and net obfuscation are proposed to achieve 100% protection against all types of scan-based attacks.…”