Design for Reliability of Wafer Level Packages

Driel, W.D. van; Hochstenbach, H.P.; Zhang, G.Q.

doi:10.1109/esime.2006.1643961

Cited by 8 publications

(6 citation statements)

References 14 publications

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“…Once the parts are diced from a wafer, they can be placed onto a printed circuit board which has screened solder paste, and reflowed into place along with other surface mount components. WLP of larger die and with a high density of contacts is very challenging [6], [7]. For the same circuit board substrate, larger die imply a larger thermo-mechanical runout during the solder reflow operation and also during operational cycles.…”

Section: Wafer-level Packaging With Solderedmentioning

confidence: 99%

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Chow

Fork

Chua

et al. 2009

IEEE Trans. Adv. Packag.

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Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm 6.5 mm with 48 spring contacts on a 0.8 mm 0.65 mm grid array, each spring measuring 400 m 100 m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone 20 000 hot plate thermal cycles and 1000 oven thermal cycles without failure.

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Section: Wafer-level Packaging With Solderedmentioning

confidence: 99%

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Chow

Fork

Chua

et al. 2009

IEEE Trans. Adv. Packag.

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“…There are very few literature published on WLP temperature cycle test [1][2][3][4]. Driel et al [1] published results on 1 st and 2 nd level reliability of WLP using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques.…”

Section: Introductionmentioning

confidence: 98%

“…Driel et al [1] published results on 1 st and 2 nd level reliability of WLP using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate were proposed to improve the solder joint fatigue life by Lee et al [2].…”

Section: Introductionmentioning

confidence: 99%

Board level temperature cycling study of large array Wafer Level Package

Rahim

Zhou

Fan

et al. 2009

2009 59th Electronic Components and Technology Conference

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The demand for Wafer Level Packages (WLP) has increased significantly due to its smaller package size and lower cost. However, board level reliability of WLP is still a major concern. This study investigates the board level temperature cycle reliability of three very different wafer level package configurations. Comprehensive studies are carried out through temperature cycle test, failure analysis, and finite element modeling. To assess the wafer level package capability and technology limit, the following parameters are considered: WLP structure, array size, ball locations, ball pitch, and temperature cycle profile.Daisy-chain chips are used for this study. Extensive failure analysis was carried out to confirm failure mechanism and quantify the mechanical degradation among different solder joints due to temperature cycle stressing. It is suggested that the primary failure mechanism is solder fatigue. The crack is in bulk solder at package side. The cracks initiate from both sides of the solder joint. The cracks propagate from edge toward the center of the solder ball. The corner balls are most susceptible to solder joint failures. Based on test data, making corner balls electrically not connected improves the WLP reliability by 30%.It is concluded that WLP structure A has superior solder joint reliability compared to B and C. For a given ball array size, smaller pitch gives better solder joint life. The solder joint fatigue life is approximately 1.2 times longer for 2 cycle per hour (cph) conditions than 1 cph temperature cycling condition.

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“…Thermal cycling test is one of the most commonly used reliability tests to assess thermo-mechanical reliability of the solder joints. The purpose of this test is to investigate the aptitude of solder joints to support mechanical stresses which is a major failure mechanism that can lead to solder joint fatigue failure [1][2][3][4][5]. The Thermo-mechanical stresses induced by alternating thermal cycles [6] are mainly induced by thermal expansion mismatch of different materials in assembly system.…”

Section: Introductionmentioning

confidence: 99%

Optimization of solder joints in embedded mechatronic systems via Kriging-assisted CMA-ES algorithm

Hamdani

Radi

Hami

2019

Int. J. Simul. Multidisci. Des. Optim.

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In power electronics applications, embedded mechatronic systems (MSs) must meet the severe operating conditions and high levels of thermomechanical stress. The thermal fatigue of the solder joints remains the main mechanism leading to the rupture and a malfunction of the complete MS. It is the main failure to which the lifetime of embedded MS is often linked. Consequently, robust and inexpensive design optimization is needed to increase the number of life cycles of solder joints. This paper proposes an application of metamodel-assisted evolution strategy (MA-ES) which significantly reduces the computational cost of ES induced by the expensive finite element simulation, which is the objective function in optimization problems. The proposed method aims to couple the Kriging metamodel with the covariance matrix adaptation evolution strategy (CMA-ES). Kriging metamodel is used to replace the finite element simulation in order to overcome the computational cost of fitness function evaluations (finite element model). Kriging is used together with CMA-ES and sequentially updated and its fidelity (quality) is measured according to its ability in ranking of the population through approximate ranking procedure (ARP). The application of this method in the optimization of MS proves its efficiency and ability to avoid the problem of computational cost.

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Design for Reliability of Wafer Level Packages

Cited by 8 publications

References 14 publications

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Board level temperature cycling study of large array Wafer Level Package

Optimization of solder joints in embedded mechatronic systems via Kriging-assisted CMA-ES algorithm

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