Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs

Abstract

in high-performance designs, a large fraction of the total numPerformance verification is critical to high-performance ber of paths after timing closure are now critical [12]. Hence, ASICs manufacturing. Performance verification ensures that an automatic test pattern generation (ATPG) tool that produces only those chips whose performance is higher than an adver-high transition fault coverage is guaranteed to exercise a large tised threshold are shipped to demanding customers. This pro-number of the critical paths in the design. At-speed transition vides a means to weed out nominal performance ASICs, and fault test with high coverage can therefore be used as a lowalso ship ASICs at difference grades. At-speed structural test cost platform for performance verification. can provide performance verification capability at very low In this paper, we present a new methodology for perforcost. In this paper, we present a scalable and flexible struc-mance verification of high-performance ASICs using at-speed tural test methodfor performance verification of ASICs. The structural test (ASST). The novel contributions of this work are tural tet methodfor perormance erlficalonasffollows.h proposed method requires no tight restrictions on the circuit as follows design. Moreover, low-cost testers are used, thus sharply re-1. The proposed methodology is highly scalable to any number ducing test cost. of logic domains-under-test. Any number of on-chip phase-1

On-Chip Structures for Fmax Binning and Optimization

“…The structural (scan-based) test includes LOC (launch on shift), LOS (launch on capture), and LOES (launch on extra shift) tests [ 11 , 12 , 13 ]. During the structural test, at-speed test patterns are shifted through scan chains with a low speed scan clock, and then, the test is performed with one or two high-speed functional clock cycles [ 14 , 15 , 16 ].…”