2007 IEEE International Test Conference 2007
DOI: 10.1109/test.2007.4437566
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Advancements in at-speed array BIST: multiple improvements

K. Gorman
1
,
Michael Roberge
2
,
A. Paparelli
3
et al.
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Cited by 3 publications
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Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs

Hsieh
1
,
Li
2
,
Wu
3
et al. 2017
2017 International Test Conference in Asia (ITC-Asia)
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Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs

Hsieh
1
,
Li
2
,
Wu
3
et al. 2017
2017 International Test Conference in Asia (ITC-Asia)
5
0
0
0
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Embedded DRAM in 45-nm Technology and Beyond

Anand
1
,
Gorman
2
,
Jacunski
3
et al. 2011
IEEE Des. Test. Comput.
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A hybrid built-in self-test scheme for DRAMs

Yang
1
,
Li
2
,
Yu
3
et al. 2015
VLSI Design, Automation and Test(VLSI-Dat)
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