Design Considerations of a Floating-Point ADC with Embedded S/H

Piper, J.; Yuan, Jiren

doi:10.1109/iscas.2005.1466048

Cited by 7 publications

(2 citation statements)

References 15 publications

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“…On the other hand, floating-point ADCs (FADCs) offer an alternative way to achieve a wide dynamic range [10][11][12]. FADCs amplify small signals before quantization as a front-end VGA that leads to enhancement of the effective resolution of low-level signals.…”

Section: Introductionmentioning

confidence: 99%

Analog to digital converter for high density neural signal recording front-end in 90 nm

Zarifi

Farshchi

Frounchi

2011

Analog Integr Circ Sig Process

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High-fidelity recording of neural signals requires varying levels of signal gain to capture lowamplitude single-unit activity in the presence of highamplitude population activity. A floating-point approach has been used to widen the dynamic range of analog-todigital converters (ADC) designed for this application. In this paper we present an ADC, designed for multi-channel, portable neural signal recording systems. To achieve low power consumption, small die area and wide dynamic range, an ADC based on a time-based algorithm, combined with a floating-point pipelined structure has been designed and simulated. A conventional variable-gain amplifier (VGA) stage has been eliminated in favor of a referencecurrent in a time-based ADC architecture. The 12-b pipelined time-based floating-point ADC has been designed with a 7-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The mantissa is determined by a uniform 7-b pipelined time-based analog to digital converter. The ADC chip was designed and simulated in a 90 nm CMOS process, which occupies an active area of 360 lm 9 550 lm, and consumes 7.8 lW at 1.2 V in full-scale conversion.

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Section: Introductionmentioning

confidence: 99%

Analog to digital converter for high density neural signal recording front-end in 90 nm

Zarifi

Farshchi

Frounchi

2011

Analog Integr Circ Sig Process

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“…Floating-point ADCs (FADCs) offer an alternative way to achieve a wide dynamic range in the analog to digital conversion [11]. These ADCs amplifies the signals with small amplitude before quantization as a front-end VGA that leads to enhancement of the effective resolution of low-level signals.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient analog to digital converter in 90nm CMOS

Zarifi

2011

2011 1st Middle East Conference on Biomedical Engineering

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Multi-electrode array devices are widely considered for sensing a large amount of neural data in implantable applications. In such systems power and area are playing most important roll in design and implementation. This paper presents a low power, variable bits and small area analog to digital converter (ADC) for biopotential and neural signals-recording applications. This work has been simulated in standard 90 nm 1P9M CMOS with sample rate of 1Ms/sec and variable precision of 7 to 12 bits. The standby (no input signal) power dissipation of the ADC is 500 nW and full-scale signal conversion is 7.8 ȝW from a single 1.2-V supply.

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analog-digital converter

Piper¹

SpringerReference

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Design Considerations of a Floating-Point ADC with Embedded S/H

Cited by 7 publications

References 15 publications

Analog to digital converter for high density neural signal recording front-end in 90 nm

Analog to digital converter for high density neural signal recording front-end in 90 nm

Energy efficient analog to digital converter in 90nm CMOS

analog-digital converter

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