Design considerations for soft embedded programmable logic cores

Wilton, Steven J. E.; Kafafi, Noha; Wu, Josephine W.; Bozman, Kimberly; Aken'Ova, V.; Saleh, R.

doi:10.1109/jssc.2004.841038

Cited by 32 publications

(53 citation statements)

References 9 publications

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“…Wilton et al [27] also examined the area and delay penalty of using programmable logic. The approach taken for the analysis was to replace part of a non-programmable design with programmable logic.…”

Section: Past Fpga To Asic Comparisonsmentioning

confidence: 99%

Measuring the Gap Between FPGAs and ASICs

Kuon

Rose

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

787

132

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This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flipflops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.

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Section: Past Fpga To Asic Comparisonsmentioning

confidence: 99%

Measuring the Gap Between FPGAs and ASICs

Kuon

Rose

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

787

132

View full text Add to dashboard Cite

show abstract

“…This gap between FPGAs and ASICs is also what FPGA architects fundamentally aim to narrow. There have been various comparisons between FPGAs or similar devices and ASICs in the past [45,214,245]. Recently, a more thorough comparison has been performed [119,120].…”

Section: The Gap Between Fpga and Asicsmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

316

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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“…However there are even more serious limitations [5]. First, every eFPGA embeds a fixed amount of reconfigurable resources.…”

Section: Introductionmentioning

confidence: 99%

Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach

Bollengier

Lagadec

Najem

et al. 2017

Lecture Notes in Computer Science

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Abstract. Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits' lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerbating timing closure issues. This article tackles these two issues and introduces the ARGen generator that produces scalable soft reconfigurable cores. The architectural template relies on injecting flip-flops into the interconnect, to favor easy and accurate timing estimation. The cores are compliant with the academic standard for place and route environment, making ARGen a one stop shopping point for whoever needs exploitable soft reconfigurable cores.

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Design considerations for soft embedded programmable logic cores

Cited by 32 publications

References 9 publications

Measuring the Gap Between FPGAs and ASICs

Measuring the Gap Between FPGAs and ASICs

FPGA Architecture: Survey and Challenges

Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach

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