Design-aware lithography

Abstract

In the face of continued technology scaling with limited lithographic capabilities, there has been a push towards increased co-optimization of design and process. A key enabler is enhancing the design-manufacturing interface to allow more information than traditional layout shapes to propagate to lithography. We describe a method to generate this additional information in the form of shape tolerances on layout polygons. We further develop two different manufacturing methods to utilize these tolerances during mask optimization. One is a tolerance-driven optical proximity correction algorithm to limit on-wafer lithographic hotspots by constraining process window contours to lie within tolerances. The second is a layout optimization approach that modifies layout shapes during OPC to make them more robust to process variations. Our experiments show that this increased level of interaction between design and lithography leads to fewer process hotspots on-wafer compared to conventional design-oblivious methods.