Design Automation for Streaming Systems

Wawrzynek, John; Caspi, Eylon

doi:10.21236/ada603902

Cited by 9 publications

(13 citation statements)

References 74 publications

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“…5. Buffers are implemented as FIFO queues using shift registers (SRLs) to take advantage of Xilinx FPGA's built-in SRL resources [20]. The split primitive looks at flit headers and routes input packets by sending them to the appropriate output port.…”

Section: A Primitive Operationmentioning

confidence: 99%

FPGA optimized packet-switched NoC using split and merge primitives

Huan

DeHon

2012

2012 International Conference on Field-Programmable Technology

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Abstract-Due to their different cost structures, the architecture of switches for an FPGA packet-switched Networkon-a-Chip (NoC) should differ from their ASIC counterparts. The CONNECT network recently demonstrated several ways in which packet-switched FPGA NoCs should differ from ASIC NoCs. However, they also concluded that pipelining was not appropriate for the FPGA switches. We show that the Split-Merge switch architecture is more amenable to pipelining on FPGAs, achieving 300MHz operation-up to three times the frequency and throughput of the CONNECT switches-with only 13-37% more area. Furthermore, we show that the Split-Merge switches are at least as efficient at routing traffic as the CONNECT switches, meaning the 2-3× frequency translates directly into two to three times the application performance.

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Section: A Primitive Operationmentioning

confidence: 99%

FPGA optimized packet-switched NoC using split and merge primitives

Huan

DeHon

2012

2012 International Conference on Field-Programmable Technology

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“…9) [14]. This flow serves a dual purpose, (1) to map an entire application to a stand-alone FPGA for single context execution, and (2) to evaluate a hypothetical, FPGA-based CP for time-shared execution.…”

Section: Operator Mapping To Fpgasmentioning

confidence: 99%

“…Analysis of queue bounds can be performed using state space exploration, composing automata for SFSMs and queues of particular capacities, and checking for deadlock states [14]. Queues that cannot be statically bounded may still be supported with dynamic allocation using BUFFER LOCK DETECTION and HANDLING.…”

Section: Inter-operator Queuingmentioning

confidence: 99%

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Stream computations organized for reconfigurable execution

DeHon

Markovsky

Caspi

et al. 2006

Microprocessors and Microsystems

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“…In this paper, we propose a unified spatial methodology based on VLIW-SCORE. We use the existing, high-level SCORE [3], [5] (Stream Computation Organized for Reconfigurable Execution) framework described in Section III and couple that to a custom, hybrid VLIW architecture described in Section III-C. This allows us to compose the complete accelerator system entirely on the parallel FPGA fabric without resorting to sequential offload or excessively burdening the programmer.…”

Section: Introductionmentioning

confidence: 99%

VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration

Kapre

DeHon

2011

2011 International Conference on Field-Programmable Technology

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Abstract-Many stand-alone, FPGA-based accelerators separate the implementation of a computation into two components -(1) a large parallel component that is realized as hardware on spatial FPGA fabric and (2) a small control and co-ordination component that is realized as software on embedded soft-core processors like an off-the-shelf Xilinx Microblaze (or host offchip CPU). While this hardware-software partitioning methodology allows the designer to lower design effort when composing the accelerator system, it introduces unnecessary Amdahl's Law bottlenecks and limits scalability. In this paper, we show how to avoid these limitations with VLIW-SCORE: a combination of a high-level parallel programming framework called SCORE and a custom, hybrid VLIW hardware organization. We demonstrate the benefits of this methodology for the SPICE circuit simulator when implementing the simulation control algorithms. With our spatial mapping flow we are able to improve performance by ≈30% (mean across circuit benchmarks) when compared to the Microblaze implementation for the Xilinx Virtex-6 LX760 FPGA. For complete application acceleration, we see an improved speedup from 1.9× for the Microblaze-based design to 2.6× for the hybrid, custom VLIW implementation when comparing a Xilinx Virtex-6 LX760 FPGA (40nm) with an Intel Core i7 965 CPU (45nm).

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Design Automation for Streaming Systems

Cited by 9 publications

References 74 publications

FPGA optimized packet-switched NoC using split and merge primitives

FPGA optimized packet-switched NoC using split and merge primitives

Stream computations organized for reconfigurable execution

VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration

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