FPGA optimized packet-switched NoC using split and merge primitives

Huan, Yutian; DeHon, André

doi:10.1109/fpt.2012.6412110

Cited by 56 publications

(20 citation statements)

References 18 publications

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“…Some have suggested that VCs consume area and power excessively [Huan and DeHon 2012]. We investigate a one-VC version of our hard NoC with hard links and find that it does, in fact, improve area per BW.…”

Section: Hard and Soft Nocsmentioning

confidence: 95%

Networks-on-Chip for FPGAs

Abdelfattah

Betz

2014

ACM Trans. Reconfigurable Technol. Syst.

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As FPGA capacity increases, a growing challenge is connecting ever-more components with the current low-level FPGA interconnect while keeping designers productive and on-chip communication efficient. We propose augmenting FPGAs with networks-on-chip (NoCs) to simplify design, and we show that this can be done while maintaining or even improving silicon efficiency. We compare the area and speed efficiency of each NoC component when implemented hard versus soft to explore the space and inform our design choices. We then build on this component-level analysis to architect hard NoCs and integrate them into the FPGA fabric; these NoCs are on average 20-23× smaller and 5-6× faster than soft NoCs. A 64-node hard NoC uses only ∼2% of an FPGA's silicon area and metallization. We introduce a new communication efficiency metric: silicon area required per realized communication bandwidth. Soft NoCs consume 4960 mm 2 /TBps, but hard NoCs are 84× more efficient at 59 mm 2 /TBps. Informed design can further reduce the area overhead of NoCs to 23 mm 2 /TBps, which is only 2.6× less efficient than the simplest point-to-point soft links (9 mm 2 /TBps). Despite this almost comparable efficiency, NoCs can switch data across the entire FPGA while point-to-point links are very limited in capability; therefore, hard NoCs are expected to improve FPGA efficiency for more complex styles of communication.

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Section: Hard and Soft Nocsmentioning

confidence: 95%

Networks-on-Chip for FPGAs

Abdelfattah

Betz

2014

ACM Trans. Reconfigurable Technol. Syst.

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“…Often a time-multiplexed overlay network can be more efficient than a packet-switched network [75]. Because of the different cost structure between ASICs and FPGAs, overlay NoCs on FPGAs should be designed differently from ASIC NoCs [76], [77]. Ultimately, it may make sense to integrate packet-switched NoC support directly into the FPGA fabric [78].…”

Section: )mentioning

confidence: 99%

Reconfigurable Computing Architectures

2015

Self Cite

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This paper provides an overview of the broad body-of-knowledge developed in the field of reconfigurable computing.ABSTRACT | Reconfigurable architectures can bring unique capabilities to computational tasks. They offer the performance and energy efficiency of hardware with the flexibility of software. In some domains, they are the only way to achieve the required, real-time performance without fabricating custom integrated circuits. Their functionality can be upgraded and repaired during their operational lifecycle and specialized to the particular instance of a task. We survey the field of reconfigurable computing, providing a guide to the body-ofknowledge accumulated in architecture, compute models, tools, run-time reconfiguration, and applications.

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“…Next, we look at the overhead of VCs by investigating a one-VC version of our hard NoC running at 0.9 V. Some have suggested that VCs consume area and power excessively [5]. Table 3 confirms that supporting multiple VCs does reduce energy efficiency.…”

Section: Comparing Nocs and Fpga Interconnectmentioning

confidence: 99%

“…Both soft NoCs [3][4][5] and hard NoCs [6,7] have been introduced in the context of FPGAs, but power consumption was seldom analyzed. However, there is an extensive body of work discussing the power consumption of NoCs for multiprocessors.…”

Section: Introductionmentioning

confidence: 99%

The power of communication: Energy-efficient NOCS for FPGAS

Abdelfattah

Betz

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Integrating networks-on-chip (NoCs) on FPGAs can improve device scalability and facilitate design by abstracting communication and simplifying timing closure, not only between modules in the FPGA fabric but also with large "hard" blocks such as high-speed I/O interfaces. We propose mixed and hard NoCs that add less than 1% area to large FPGAs and run 5-6× faster than the soft NoC equivalent. A detailed power analysis, per NoC component, shows that routers consume 14× less power when implemented hard compared to soft, and whether hard or soft most of the router's power is consumed in the input modules for buffering. For complete systems, hard NoCs consume less than 6% (and as low as 3%) of the FPGA's dynamic power budget to support 100 GB/s of communication bandwidth. We find that, depending on design choices, hard NoCs consume 4.5-10.4 mJ of energy per GB of data transferred. Surprisingly, this is comparable to the energy efficiency of the simplest traditional interconnect on an FPGA -soft point-to-point links require 4.7 mJ/GB. In many designs, communication must include multiplexing, arbitration and/or pipelining. For all these cases, our results indicate that a hard NoC will be more energy efficient than the conventional FPGA fabric.

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FPGA optimized packet-switched NoC using split and merge primitives

Cited by 56 publications

References 18 publications

Networks-on-Chip for FPGAs

Networks-on-Chip for FPGAs

Reconfigurable Computing Architectures

The power of communication: Energy-efficient NOCS for FPGAS

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