VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration

Abstract

Abstract-Many stand-alone, FPGA-based accelerators separate the implementation of a computation into two components -(1) a large parallel component that is realized as hardware on spatial FPGA fabric and (2) a small control and co-ordination component that is realized as software on embedded soft-core processors like an off-the-shelf Xilinx Microblaze (or host offchip CPU). While this hardware-software partitioning methodology allows the designer to lower design effort when composing the accelerator system, it introduces unnecessary Amdahl's Law bottlenecks and limits scalability. In this paper, we show how to avoid these limitations with VLIW-SCORE: a combination of a high-level parallel programming framework called SCORE and a custom, hybrid VLIW hardware organization. We demonstrate the benefits of this methodology for the SPICE circuit simulator when implementing the simulation control algorithms. With our spatial mapping flow we are able to improve performance by ≈30% (mean across circuit benchmarks) when compared to the Microblaze implementation for the Xilinx Virtex-6 LX760 FPGA. For complete application acceleration, we see an improved speedup from 1.9× for the Microblaze-based design to 2.6× for the hybrid, custom VLIW implementation when comparing a Xilinx Virtex-6 LX760 FPGA (40nm) with an Intel Core i7 965 CPU (45nm).

On Data Forwarding in Deeply Pipelined Soft Processors

“…Although a hard processors such as the PowerPC CPUs in Virtex-2 Pro and the ARM cores in the newer Zynq SoCs can o↵er better performance than an equivalent soft processor, they are inappropriate for situations where lightweight control and co-ordination [13] are required. Their fixed position in the FPGA fabric can also complicate design, and they demand supporting infrastructure for logic interfacing.…”

“…Processors find extensive use within FPGA systems, from management of system execution and interfacing, to implementation of iterative algorithms outside of the performancecritical datapath [13]. In recent work, soft processors have been demonstrated as a viable abstraction of hardware resources, allowing multi-processor systems to be built and programmed easily.…”

Optimizing stream program performance on CGRA-based systems

“…Stream graphs have been mapped to different architectures, including the Cell processor [20], GP-GPUs [12,21], FPGA [22,23], and other reconfigurable architectures [24]. Those techniques often focus on exploiting task-level parallelism (TLP) and balancing workloads among multiple processors.…”

TILT: A multithreaded VLIW soft processor family

“…[4] describe a VLIW soft processor that can be dynamically reconfigured (using Xilinx partial reconfig support) to be either a single 4-wide core or two 2-wide cores. Most closely related is VLIW-SCORE [1], a VLIW, pipelined architecture for utilizing floating point units, that compiler-schedules operations via software pipelining. One key difference vs TILT is storage organization: VLIW-SCORE organizes storage as a pair of operand memories in front of each functional unit, with a time-multiplexed network connecting functional unit outputs to operand-memory inputs; in contrast, TILT organizes storage as banks of memory having contiguous per-thread address spaces.…”