Design and performance evaluation of a low transistor ternary CNTFET SRAM cell

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

“…Also, its leakage‐current and powers are still smaller than ‘all 6T bitcells in Table 1’ and ‘other 8T bitcells in Table 2’. Maybe it seems that using 11 Transistors causes some foot‐print problems, but note that other works utilised 10, 11, 16, 18, 20 and even 22 Transistors in their bitcells without any problems [12, 13, 15, 19, 20, 23, 28, 33, 58, 68]. As a result, the 11T design in Figure 9 is the optimum SRAM‐bitcell that this study tries to obtain it by solving the challenges.…”

“…In fact, this feature of power‐gating and also the idea of employing output inverter in read path, lead to have a stable bitcell with small powers, compared to other works (Tables 1–3). Other works often reduced delays at the cost of higher power‐consumptions [10–75].…”

“…Also, it has an acceptable leakage current and static/dynamic powers (Table 3). Note that other works were not designed for operating at threshold supply‐voltage ($${V}_{\text{DD}}$$ = $${V}_{\text{th}}$$), as well as, they just reduced their delays at the cost of higher power‐consumptions [10–75] which are not suitable for implementing in chipset of portable devices. As a result, this 11T bitcell (Figure 9) can be considered as a final optimum design that this paper tries to reach it from the beginning.…”

“…In recent decades, many efforts have been made by researchers to offer optimum designs for bitcell. They declared that thanks to the CNTs, CNTFETs have been considered as a promising alternative for Complementary Metal Oxide Semiconductors (CMOSs) in low power SRAMs [10–75], however, CNFET fabrication process still has some imperfections, including the presence of metallic carbon nanotubes ( m ‐CNTs), imperfect m ‐CNT removal processes, chirality drift, CNT doping variations, and density fluctuations, etc. [76–79].…”

“…Although several studies employed ‘decoupled R/W BLs’ and ‘power‐gating’ techniques, none of them referred to this paperʼs point. If it seems that using 11 Transistors causes some foot‐print problems, you should note that previous works utilised more than 11 Transistors without any problems [12, 13, 15, 19, 20, 23, 28, 33, 58, 68]. The following analysis and simulations are done by HSpice, CNTFET Stanford Model, and Monte‐Carlo Method.…”