Image processing is an important task in data processing systems for applications such as medical sectors, remote sensing, and microscopy tomography. Edge recognition is a sort of image division method that is used to simplify the image records so as to reduce the amount of data to be processed. Edges are considered the most important in image processing because they are used to characterize the boundaries of an image. The performance of the Canny edge recognition algorithm remarkably surpasses the present edge recognition technology in various computer visualization methods. The main drawback of using Canny edge boundary is that it consumes lot of period due to its complex computation. In order to tackle this problem a hybrid edge recognition method is proposed in block stage to locate edges with no loss. It employs the Sobel operator estimate method to calculate the value and direction of the gradient by substituting complex processes by hardware cost savings, traditional non-maximum suppression adaptive thresholding block organization, and conventional hysteresis thresholding. Pipeline was presented to lessen latency. The planned strategy is simulated using Xilinx ISE Design Suite14.2 running on a Xilinx Spartan-6 FPGA board. The synthesized architecture uses less hardware to detect edges and operates at maximum frequency of 935 MHz.
Low-power IC design has become a priority in recent years because of the growing proliferation of portable battery-operated devices, bringing Static Random-Access Memory (SRAM) and Content Addressable Memory (CAM) into play. In today's SoCs, embedded SRAM units have become a necessary component. There is a lack of chips in the current world and to manufacture chips there is the requirement of Electronic Design Automation(EDA) tools that can perform better. In this paper, the main motive is to showcase the performance of open-source tools available currently which can still generate the required output with no cost. In this new era of fast mobile computing, traditional SRAM cell designs are power-demanding and underperforming. Rather than lowering manufacturing costs through high-volume production, specialty memory give cost-effective alternatives through architecture. Specialty memory devices enable the designer to address issues like board area, important timing, data flow bottlenecks, and so on in ways that high-volume regular memory devices cannot. Implementation of memory devices on Cadence environment and open-source environment to check the compatibility and compare the power, area, and delay of both 64-bit SRAM and CAM also analysing and validating the results of both the memory devices in this paper. For SRAM in a cadence environment, the calculated power, area, and slack have improved values, namely 0.145mW, 1104.3um2, and positive slack of 6636. Furthermore, the power for 64-bit CAM in a cadence context is nearly identical to those for an open-source environment ~0.8mW. In an open-source environment, the calculated slack for CAM is 4.74.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.