Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

Venkataiah, C.; Ramanjaneyulu, N.; Rao, Y. Mallikarjuna; Prakash, V. N. V. Satya; Murthy, M. K. Linga; Rao, N. Srinivasa

doi:10.1007/s41204-022-00249-x

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2022

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“…As VLSI advancements into sub-micron interconnect wire will play an important role in the overall delay performance and analysis of power consumption of better chips. Interconnect transmission delay will have more impact device delay and make a performance bottleneck [1][2][3][4][5]. For a greater number of interconnect wires and their amount of resistance and resources may require lot to drive the wires may also increases.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Analysis of On-chip VLSI Interconnects

Jayamma¹,

Ramanjaneyulu²,

Sathish³

et al. 2022

International Journal of Emerging Research in Engineering, Science, and Management

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In this paper dynamic crosstalk is analyzed for coupled on-chip VLSI interconnects in different conditions. The proposed work has taken the MOS transistor analytical expressions. In this work, calculated the transition delays and different timings of the interconnect aggressor and interconnect victim drivers for in-phase switching and out-of-phase switching. All the calculated results are compared with simulations in SPICE. The average error in the transmission delay using SPICE is 2.02 and 3.274% for the interconnect aggressor and interconnect victim buffers for in phase switching, respectively. The average errors in the same are 2.3 and 1.87% for out phase switching event.

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