Design and performance analysis of low power LNA with variable gain current reuse technique

Kalra, Dheeraj; Goyal, Vishal; Srivastava, Mayank

doi:10.1007/s10470-021-01855-6

Cited by 6 publications

(1 citation statement)

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“…Input impedance at the input terminal is the series combination of resistive capacitive and inductive term and given by equation (3) Using conventional method Therefore, PSO algorithm is used. In which objective function include the NF and gain function is given as [22][23][24][25].…”

Section: Formulamentioning

confidence: 99%

Design Optimization of LNA using PSO algorithm with Multi Stage Noise Matching Technique for UWB Application

Kumar

Kalra

Shukla

2023

Preprint

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This manuscript describe optimization of LNA using PSO algorithms. The proposed LNA consist of two stage cascading. In the first stage current reused technique has been used using complementary MOS. Both the MOS use the common biasing current, henceforth saving a lot of power. While second stage is the cascading of two NMOS transistors, to increase the overall gain. Since traditional method of impedance matching is not sufficient to reduce the Noise Figure(NF). Therefore, an approach aiming to minimize high band noise has been used at the cost of increase in NF minimum. All the passive elements and aspect ratio are optimized through PSO in which objective function consist of NF and voltage gain term. Number of iterations used in PSO algorithm is 1500. LNA is simulated in 45 nm CMOS Technology for a wide range of frequency from 1GHz to 20GHz. Simulation show minimum NF of 1.89 Db, power gain(S21) and input reflection coefficient(S11) 16.8dB and − 19.2dB. Process corner simulation for robust ness of LNA has been done and depicted ten percent variation around the typical value of LNA. The power consumption of 32 mW and chip area order of 2.2mm × 1.6mm with core area is 650 µm in layout design.

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Section: Formulamentioning

confidence: 99%