Design and performance analysis of a high speed AWGN communication channel emulator

Ghazel, Adel; Boutillon, Emmanuel; Danger, Jean‐Luc; Gulak, Glenn; Laamari, H.

doi:10.1109/pacrim.2001.953647

Cited by 41 publications

(38 citation statements)

References 1 publication

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“…These FPGA prototype results exactly match the results obtained with a software model. These performance tests used an emulated Gaussian channel [14]. Table I shows the application-specific integrated circuit implementation results for our decoder in 0.13-µm CMOS, alongside the BS approximate MS decoder in [5].…”

Section: Implementation Resultsmentioning

confidence: 99%

A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding

Cushon

Leroux²,

Hemati³

et al. 2010

IEEE Trans. Circuits Syst. II

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Abstract-In this brief, we introduce a new iterative decoder implementation called pulsewidth-modulated min-sum (PWM-MS), in which messages are exchanged in a pulsewidth-encoded format. The advantages of this method are low switching activity, very low complexity check nodes, low routing congestion, and excellent energy efficiency. We implement a fully parallel PWM offset MS decoder for a (660, 484) regular (4, 15) low-density parity-check code with 4-bit quantization in 0.13-µm CMOS, with a core area of 5.76 mm 2 (4.24-mm 2 cell area or 556K equivalent AND gates). In postlayout simulations, this decoder achieves an average information throughput of 5.71 Gb/s and an energy consumption of 65.8 pJ per information bit at a signal-to-noise ratio of 5.5 dB. Our results show a 21% reduction in area, a 0.6-dB improvement in coding gain, and an energy efficiency improvement of 19% over the comparable bit-serial MS decoder architecture. We also demonstrate 3-bit implementations, in which the coding gain is traded off for further improvements in throughput, area, and energy efficiency.Index Terms-Low-density parity-check (LDPC) codes, low power, low switching activity, min-sum (MS) iterative decoding, pulsewidth modulation (PWM).

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Section: Implementation Resultsmentioning

confidence: 99%

A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding

Cushon

Leroux²,

Hemati³

et al. 2010

IEEE Trans. Circuits Syst. II

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show abstract

“…The most relevant publications in this area are [5]- [7], which implement AWGN generators in FPGAs. These existing solutions are mainly based on the Box-Muller method.…”

Section: A Existing Methods Of Awgn Generationmentioning

confidence: 99%

“…An FPGA implementation of the Box-Muller method is proposed in [5], where implementing ln and cos functions requires careful consideration with regard to the number of recursions and relative position of points, as well as the precision of implementation. The efficient implementation is therefore not straightforward.…”

Section: A Existing Methods Of Awgn Generationmentioning

confidence: 99%

“…For a digital system where data "0" and "1" are transmitted, the maximum output of the noise generator is generally required to be bigger than 0.5 to generate bit errors. The existing hardware AWGN generators (e.g., [5]- [7]) have a maximum output value of 7. If we use such generators in baseband transmission, they can only generate a theoretical maximum SNR of 16.9 dB by being scaled by a factor of 14 (see Section VI-B).…”

Section: A Ber and Snrmentioning

confidence: 99%

“…For an AWGN emulator, the tail is bounded by its maximum output value m, which determines the maximum signal-to-noise ratio (SNR) that the AWGN system can generate. Although there exist stand-alone AWGN generators, their m value is less than 7 [5]- [7]. Their tail distribution accuracy needs to be improved for very low BER applications.…”

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confidence: 99%

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BER Testing of Communication Interfaces

Fan

Žilić

2008

IEEE Trans. Instrum. Meas.

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Abstract-This paper presents a versatile bit-error-rate (BER) testing scheme to characterize the quality of communication interfaces. Traditionally, the presilicon BER is evaluated using time-consuming software simulations. The stand-alone BER test products for postsilicon evaluation are expensive and do not include channel emulators, which are essential to testing the BER under the presence of noise. For both the design and evaluation phases, we present a scheme for BER testing in fieldprogrammable gate arrays (FPGAs) that consists of a BER tester (BERT) core and a novel additive white Gaussian noise (AWGN) generator core. The maximum output value of our AWGN generator is 53, whereas that of the existing solutions is less than 7. Therefore, our generator can better emulate the tail of a Gaussian distribution, which is suitable for exploring applications at very low BERs. We also present a pipelined structure that exploits the central limit theorem for speedups of four or more. Combining a BERT and an AWGN in FPGAs is orders of magnitude more efficient in cost, volume, and energy over the existing similar-speed stand-alone solutions and has a huge speed advantage over software simulations. We demonstrate the applications of our solution through two case studies. Index Terms-Additive white Gaussian noise (AWGN), bit error rate (BER), clock/data recovery (CDR), polar method, signalto-noise ratio (SNR).

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Accelerating Test, Validation and Debug of High Speed Serial Interfaces

Fan¹,

Žilić²

2011

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Design and performance analysis of a high speed AWGN communication channel emulator

Cited by 41 publications

References 1 publication

A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding

A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding

BER Testing of Communication Interfaces

Accelerating Test, Validation and Debug of High Speed Serial Interfaces

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