Accelerating Test, Validation and Debug of High Speed Serial Interfaces

Abstract

Ivan and Pauline Zilic doing their share to together depict the effects of the jittery clock in an appealing and a surprisingly lucid way.Last but not least, we would like to thank our whole families for their love and support over the years. Without their support, it would be impossible to undertake all the work and finally write the book.

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

“…greater than the one measured by the bench [15]. The transmitter jitter testing scheme presented in [31] is not very accurate; the random and deterministic jitters reported are respectively 1~2ps and 20ps greater than what measured by the bench equipment.…”

“…Today, there are not many systems that can perform jitter compliance testing for multi-gigabit devices in production [15]. greater than the one measured by the bench [15].…”

“…The transmitter jitter testing scheme presented in [31] is not very accurate; the random and deterministic jitters reported are respectively 1~2ps and 20ps greater than what measured by the bench equipment. Also, test parameters can be further optimized to achieve better test economy [15].…”

“…In order to derive the deterministic and random jitter (RJ) components, we need to work backwards [15].…”

“…Separating jitter components, allows estimating peak-to-peak jitter values at very low BER levels that would otherwise take too much time to measure directly [15][27]. An additional benefit of this technique is that it helps diagnose and understand the underlying causes of jitter [28] .…”