A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding

Abstract

Abstract-In this brief, we introduce a new iterative decoder implementation called pulsewidth-modulated min-sum (PWM-MS), in which messages are exchanged in a pulsewidth-encoded format. The advantages of this method are low switching activity, very low complexity check nodes, low routing congestion, and excellent energy efficiency. We implement a fully parallel PWM offset MS decoder for a (660, 484) regular (4, 15) low-density parity-check code with 4-bit quantization in 0.13-µm CMOS, with a core area of 5.76 mm 2 (4.24-mm 2 cell area or 556K equivalent AND gates). In postlayout simulations, this decoder achieves an average information throughput of 5.71 Gb/s and an energy consumption of 65.8 pJ per information bit at a signal-to-noise ratio of 5.5 dB. Our results show a 21% reduction in area, a 0.6-dB improvement in coding gain, and an energy efficiency improvement of 19% over the comparable bit-serial MS decoder architecture. We also demonstrate 3-bit implementations, in which the coding gain is traded off for further improvements in throughput, area, and energy efficiency.Index Terms-Low-density parity-check (LDPC) codes, low power, low switching activity, min-sum (MS) iterative decoding, pulsewidth modulation (PWM).

Post and pre-layout analysis of Low Density Parity Check (LDPC) decoder using 120nm technology Cadence Encounter Tool

“…Moreover, it requires much simpler hardware for the check node functions compared to SP decoding [5]. In the MS decoding, similar to SP algorithm [6], the extrinsic messages are passed between check and variable nodes in the form of log-likelihood ratios (LLRs).…”

“…Encoder uses generator matrix to encode the information bits in to the code word [6]. Both generator and parity check matrix are in inter related, parity check matrix is given by H=[A | I n-k ]and generator matrix is given by G=[I K | A T ].Initially parity check matrix is generated ,using that matrix generator matrix is created by Gaussian elimination method.…”

“…The matrix H is put into this form by applying elementary row operations which are interchanging two rows or adding one row to another modulo 2 [6].…”

“…Low density parity check (LDPC) decoder [3] is based under Min-Sum algorithm that has been already discussed above and for Verilog simulation,we integrate both the variable node units(VNU) and check node units(CNU) and analysis the results in ModelSim [6]. The block diagram of LDPC Decoder is shown above in figure 3.…”

“…In this paper [6],bit Flipping decoding algorithm is used. This algorithm is based on hard decision message passing algorithm.…”