Design and optimization of low voltage high performance dual threshold CMOS circuits

Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

“…Gated-V dd can be coupled with a dual-threshold voltage (dual-V t ) process technology to achieve even larger reductions in leakage [9]. SRAM cells use low-V t transistors to maintain high speed and the gated-V dd transistors use high-V t to achieve additional leakage reduction.…”

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing

“…To eliminate the glitch power, additional ILP constraints determine the positions and values of the delay elements to be inserted to balance path delays. Unlike the heuristic algorithms [2][3][4][5], this ILP gives us a globally optimal solution.…”

“…Dual-V th assignment [2][3][4][5][6] is an efficient technique to decrease leakage power. Wei et al [3] describe an algorithm to find the optimal high V th for different circuit structure.…”

“…Wei et al [3] describe an algorithm to find the optimal high V th for different circuit structure. However, in reality, the available threshold voltages in a process are predetermined and a designer does not have the choice of arbitrary V th .…”

“…However, in reality, the available threshold voltages in a process are predetermined and a designer does not have the choice of arbitrary V th . The back trace algorithm [3] used to determine the dual-V th assignment also has a disadvantage. Because the back trace search direction for non-critical paths is always from primary outputs to primary inputs, the gates close to the primary outputs always have the priority to be assigned high V th , even though their leakage power reduction due to V th increase may be smaller than that of gates close to the primary inputs.…”