Design and Measurement of a CT $\Delta\Sigma$ ADC With Switched-Capacitor Switched-Resistor Feedback

Analysis of exponentially decaying pulse shape DACs in continuous-time sigma-delta modulators

“…The jitter effect on γ is rarely treated in the CT ΣΔ literature. To the best of our knowledge, only in [3] [8] this issue is studied which shows that large delay line jitter can be allowed without significantly decreasing the SNDR. Nevertheless, the readers should be awared that this insensitivity to the delay line jitter, γ, can be validated by both simulation and measurement results, only in their particular case.…”

“…We can appreciate from (5) that the jitter induced in-band-noise (IBN) of each DAC feedback is not only dependent on its charge error variance but also on its feedback coefficient. For better comparison, two performance metrics are applied in this work, namely amplitude efficiency [3], η a , and jitter immunity, η j .…”

“…Consequently, the SCR feedback imposes stringent speed requirements on the 1 st integrator. Based on the SCR DAC architecture, several follow-up works have been reported lately: the switched-capacitor switched-resistor (SCSR) [3] ( Fig. 1(c)), the full clock period SCR (FSCR) [4] (Fig.…”

“…1(e)) architectures. Among them, [3] and [5] focus on relaxing the slew-rate requirement of the amplifier in the 1 st integrator; while [4] mainly aims to further reduce the jitter induced noise. In this paper, a full clock period SCSR (FSCSR) DAC feedback waveform is a)…”

Analysis and Modeling of Clock-Jitter Effects in Delta-Sigma Modulators

“…However, the increased peak current of the SCR DAC, given by (28), adds higher requirements on the SR and the GBW of the loop filter integrator [4,10]. Moreover, CT ΔƩ modulators using SCR DACs have poor inherent antialiasing compared to those using current-steering DACs [11] due to the loading of the SCR DAC on the integrating amplifier input nodes.…”