Design And Implementation of Low Power Phase Frequency Detector For Phase Lock Loop

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

“…Fig. 9 infers that the proposed PFD without reset consumes a power of 174 µW in comparison to that of [8] which consumes 356.5 µW at 1 GHz. At lower frequencies, the usage of the proposed PFD without a reset path has a very slight effect on the reduction of power consumption, but as the frequency of operation changes to higher values, there is significant difference in the power consumption between the architecture in [8] and the proposed PFD without a reset path.…”

“…The first classification consists of architectures from [6] and the proposed pass transistor-based PFD with AVLG. The second class consists of architecture from [8] and the proposed PFD without reset path.…”

“…For frequencies in the megahertz to the gigahertz range, there is a change in the trend of power consumption, where the existing pass transistor-based consumes lesser power than the AVLG-based PFD. The architecture of PFD from [8] and the proposed PFD without reset path have been discussed in this section and their graphical comparison in terms of power consumption in µW has been represented at frequencies ranging from 1 to 4 GHz. Fig.…”

“…Thus, the concept of reset path has to be replaced. The technique of replacing the reset path is discussed in [8]. This technique includes reference clock and VCO clock being shared among the upper part and the lower part of the PFD.…”

“…The usage of this reset path may be cumbersome sometimes due to increase in the usage of transistor which further increases the area consumed. Thus, the reset path can be replaced by sharing the reference clock and VCO clock signal in the initial stages itself [8]. This concept of replacing the reset path is carried out and a new design of PFD is proposed.…”