Design and Implementation of an Efficient Instruction Set for Ternary Processor

Narkhede, S. S.; Kharate, G. K.; Chaudhari, Bharat S.

doi:10.5120/14536-2980

Cited by 6 publications

(9 citation statements)

References 11 publications

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“…Figure 4 shows the block diagram of ternary processor, which has instruction decoder, array of registers, TALU as building blocks of data path unit. The necessary control signals to control the operations of these units are generated by ternary timing and control unit [12]. Fig.…”

Section: Fig 3 Comparison Table In Terms Of τmentioning

confidence: 99%

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A Brief Review on Multiple-Valued Logic-based Digital Circuits

Nagarathna

2021

Smart Innovation, Systems and Technologies

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Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.

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Section: Fig 3 Comparison Table In Terms Of τmentioning

confidence: 99%

“…Fig. 4 Architecture of 4 trit processor [12] 4 Quaternary Logic Circuits Songpol Ongwattanakul et al presented design of ALU to carry out addition and multiplication operations on quaternary signed Digits (QSD). The design is implemented on Altera FLEX10K using VHDL.…”

Section: Fig 3 Comparison Table In Terms Of τmentioning

confidence: 99%

A Brief Review on Multiple-Valued Logic-based Digital Circuits

Nagarathna

2021

Smart Innovation, Systems and Technologies

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“…In a D flip-flop the next state Q(t+1) is characterized by a function of both the current state Q(t) and the D data input. The next state Q(t+1) could be defined by: (12) or (13) these two equations can be transformed in a fuzzy domain by replacing the binary operators by fuzzy operators as shown in [20] [6]. Using min-max type operation and fuzzy negation we can write the following transformation:…”

Section: B Basic Element For An Mvl Memorymentioning

confidence: 99%

“…The ability to build any circuit in MVL will allow to build processors, memories and I/O devices able to operate, with the same number of connections, at a greater throughput compared to the binary case. The ternary logic was the first studied extension of the binary algebra ( [10] and [11]), but also inspired the realization of processors working on the base 3 [12]. Also the quaternary logic, being power of two, inspired many research works ( [13] and [14]).…”

Section: Introductionmentioning

confidence: 99%

Designing Digital Circuits in Multi-Valued Logic

Simonetta

Paoletti²

2018

International Journal on Advanced Science, Engineering and Information Technology

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In the last few decades we have witnessed an increase in CPU performance, which has been made possible thanks to the increase in the clock frequency and the increase in the number of transistors in the unit of space. In the last few years, however, we reached the limit for the clock and for the miniaturization of the transistor grid. Beyond this growth new problems arose such as the disposal of the produced heat and the minimum distance to be respected between elements for the electrical signals transfer. So the chip makers, to further increase the processing power of the processors, started to insert more cores on the same chip. The presence of several cores undoubtedly improves performance and improves consumption, but the ability to transfer data between cores and components remains limited by the number of pins of the cores themselves. Furthermore, it is necessary to manage the synchronization between cores during the access to common resources and all those multi-core architectures typical problems. This article provides a different approach to improve the computing capacity of the CPUs that is based on the extension of the binary system in a multi-value coding system or, commonly, called MVL. Although this direction has already been explored, the idea behind the study is in the representation of the generic function in the MVL domain. This representation has a link to the binary system and a surprisingly greater simplicity of the corresponding digital circuits (combinatorial and sequential). A different mathematical approach is thus provided for the realization of the multivalue logic gates. This could enable the use of different data encoding systems no longer linked to the voltage value of a signal but to other physical quantities as it happens at present, for example, in the world of telecommunications.

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“…In this work, we introduce advanced design and evaluation frameworks to realizing ternary processors, measuring actual performances with the practical benchmark programs. In contrast that the previous studies only present limited concepts to only test processing blocks in ternary number systems [13], [14], we develop a 9-trit advanced RISC-based ternary (ART-9) core by adopting the proposed frameworks, presenting the fully-functional top-level ternary microprocessor. Based on the 9-trit instruction-set architecture (ISA) with 24 custom ternary instructions, more precisely, the proposed softwarelevel framework provides an efficient way to convert the existing binary programs to the ternary codes, even reducing the program size compared to the baseline codes with RV-32I ISA [15].…”

Section: Introductionmentioning

confidence: 99%

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor

Kam¹,

Min²,

Yoon³

et al. 2021

Preprint

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In this paper, we introduce the design and verification frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06 × 10 6 DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.

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Design and Implementation of an Efficient Instruction Set for Ternary Processor

Cited by 6 publications

References 11 publications

A Brief Review on Multiple-Valued Logic-based Digital Circuits

A Brief Review on Multiple-Valued Logic-based Digital Circuits

Designing Digital Circuits in Multi-Valued Logic

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor

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