Design and implementation of 4-bit Vedic Multiplier

Maiti, Anannya

doi:10.18535/ijetst/v3i05.06

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…From table 2, it can be seen that the area and power consumption using MUX based multiplier is less compared to other Vedic multipliers. Also the performance of Vedic multiplier is high compared to array multiplier or other multiplier architectures [8][9][10].…”

Section: B Results and Comparison With Existing Architecturementioning

confidence: 99%

Design and Implementation of a Low Power Vedic Multiplier

Johny¹

2018

IJRASET

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This paper proposes the design of a low power Vedic Multiplier using the technique of Vedic Mathematics that has been modified to reduce the power consumption.Vedic multiplier is based on a novel concept in which the partial products are generated using concurrent additions. In this paper an 8 bit Vedic multiplier is designed using four 4 bit Vedic multipliers and various adder circuits. The adder circuits are realized using mux based adders instead of conventional adders as in normal Vedic multipliers. The 8×8 Vedic Multiplier circuit is coded in verilog, synthesized and simulated using Cadence Software. The power consumption and area of the multiplier using MUX based adders are compared with existing ones. Results show that the power consumption is reduced by 41% when compared to conventional Vedic multipliers and the results appear to be promising. The combination of low power and lesser area makes the new multiplier a viable option for implementing low power designs.

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Section: B Results and Comparison With Existing Architecturementioning

confidence: 99%

Design and Implementation of a Low Power Vedic Multiplier

Johny¹

2018

IJRASET

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“…We apply the proposed circuits into 4-bit array multiplier which consists of sixteen NANDs, sixteen buffers, six full adders and four half adders as shown in Fig. 12 [30,31,32]. A0 to A3 and B0 to B3 are input signals while P7 to P0 are the outputs.…”

Section: Bit Multipliermentioning

confidence: 99%

Non-floating and low-power adiabatic logic circuit

Han

Takahashi

Sekine

2019

IEICE Electron. Express

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This paper proposes a new adiabatic logic. Adiabatic logic is a good method to reduce power consumption. Several common adiabatic logics suffer from floating output which results in lack in robustness, by using the periodic power supply. At first, we analyze the floating phenomenon of previously proposed 2PC2AL in this paper. The proposed adiabatic logic can prevent the floating of the nodes to add two logic switches between the power supply and charging-discharging transistor. This paper also reports a comparison of energy dissipation between the different adiabatic logics such as, ECRL, 2N2N2P, 2PASCL, 2PC2AL, and the proposed circuit. In the SPICE simulation, the target application is a 4-bit multiplier for IoT products. Through the simulation, the output of the proposed circuit with cascade connection has a stable function.

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“…Multiplication plays a crucial role in Digital Signal Processing and for faster FFT we require a high speed multiplication block [6][7]. High speed multiplication block is implemented by using three main steps: first step: generation of partial products, second step: addition of partial product which is done with the help of adder and speed of the circuit is derived from this stage and in the last stage: final result is generated by adding two-row output.…”

Section: Multipliermentioning

confidence: 99%

High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier

Thakur¹,

Sohal²,

Jain³

2018

IJET

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In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Design suite.

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Design and implementation of 4-bit Vedic Multiplier

Cited by 5 publications

References 3 publications

Design and Implementation of a Low Power Vedic Multiplier

Design and Implementation of a Low Power Vedic Multiplier

Non-floating and low-power adiabatic logic circuit

High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier

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