Design and Implementation of a Low Power Vedic Multiplier

Abstract

This paper proposes the design of a low power Vedic Multiplier using the technique of Vedic Mathematics that has been modified to reduce the power consumption.Vedic multiplier is based on a novel concept in which the partial products are generated using concurrent additions. In this paper an 8 bit Vedic multiplier is designed using four 4 bit Vedic multipliers and various adder circuits. The adder circuits are realized using mux based adders instead of conventional adders as in normal Vedic multipliers. The 8×8 Vedic Multiplier circuit is coded in verilog, synthesized and simulated using Cadence Software. The power consumption and area of the multiplier using MUX based adders are compared with existing ones. Results show that the power consumption is reduced by 41% when compared to conventional Vedic multipliers and the results appear to be promising. The combination of low power and lesser area makes the new multiplier a viable option for implementing low power designs.