Design and Hardware Implementation of a Novel Smart Antenna Algorithm Using TI DSPs

Kavak

Karakoc

et al. 2008

Wireless Pers Commun

Development of practical algorithms for beamforming in 3G CDMA systems and their software radio implementations are still a challenging task, which will facilitate upgrading of traditional base stations into smart antenna capable 3G base stations. In this paper, we propose a practical space-code correlator (SCC) receiver structure for its software radio implementation a DSP. SCC's advantage comes from the fact that it doesn't require any training sequence or learning parameter as in other algorithms (LMS or CM). DSP implementations of the SCC are performed using Texas Instruments C67xx family platforms. In the simulations, reverse link base band signal format of CDMA2000 is used and the effects of different array topologies (uniform linear array-ULA or uniform circular array-UCA) are considered. The implementation results regarding beamforming accuracy, weight vector computation time (execution time), search resolution effect on DOA estimation accuracy, DSP resource utilization, and received SINR are presented. The results show that DSP based SCC beamformer can estimate weight vectors within less than 10 ms with DOA search resolution of 2 • especially when C6713 DSP is used. With faster DSPs and 123 246 K. Kucuk et al. larger search resolutions, execution time could be significantly reduced as well. It provides comparable SINR performance with LMS and CM algorithms.

Section: Contribution Of This Workmentioning

confidence: 99%

Section: Signal-to-interference Plus Noise Ratio (Sinr)mentioning

confidence: 99%

See 1 more Smart Citation

A Practical Space-Code Correlator Receiver for DSP Based Software Radio Implementation in CDMA2000

Kavak

Karakoc

et al. 2008

Wireless Pers Commun

“…We implement Least Mean Squares (LMS), Constant Modulus (CM), and our previously proposed practical Space Code Correlator (SCC) [14][15][16] based beamformers for CDMA2000. We evaluate their performance in terms of beamforming accuracy, FPGA resource utilization and convergence time.…”

Section: Introductionmentioning

confidence: 99%

FPGA Based Implementation and Comparison of Beamformers for CDMA2000

Dikmese

Kavak

et al. 2009

Wireless Pers Commun

For the integration of smart antennas into third generation code division multiple access (CDMA) base stations, it still remains as a challenging task to implement smart antenna algorithms on programmable processors. In this paper, we study implementations of some CDMA compatible beamforming algorithms, namely least mean square (LMS), constant modulus (CM), and space code correlator (SCC) algorithms, using Xilinx's Virtex family FPGAs. This study exhibits feasibility of implementing even simple, practical, and computationally small algorithms based on today's most powerful FPGA technologies. 16 and 32 bits floating point implementations of the algorithms are investigated using both Virtex II and Virtex IV FPGAs. CDMA2000 reverse link baseband signal format is used in the signal modeling. Randomly changing fading and Direction-of-arrivals (DOAs) of multipaths are considered as a channel condition. The implementation results in terms of beamforming 123 234 S. Dikmese et al.accuracy, FPGA resource utilization, weight vector computation time, and DOA estimation error are presented. Beamformer weight vectors using LMS and CM can be computed within less than 20 µs on Virtex II FPGA and 10 µs on Virtex IV FPGA, and using SCC it can be achieved within less than 22 µs on Virtex IV FPGA. These results show that FPGAs provide approximately 500 times faster speed in implementations than our previous work with DSPs.

“…Because, when implemented on programmable processors, these algorithms will facilitate upgrade of existing 3G base stations into smart antenna capable base stations. For this purpose, this paper has focused on implementation of CDMA-FDD adaptable antenna array algorithms which are least mean square (LMS) [6] and space code correlator (SCC) algorithms [7] on an FPGA (such as Virtex II Pro FG456 Proto Board) instead of on DSP and compared floating point DSPs implementations (such as Texas Instruments' C6701 EVM, C6711 DSK, and C6713 DSK [8]). DSP implementations are optimized and updated according to previous study [7].…”

Section: Introductionmentioning

confidence: 99%

A Comparative Study of Antenna Array Algorithm Implementations using FPGA and DSP for cdma2000

Şahin

Dikmese

2006 3rd International Symposium on Wireless Communication Systems

et al. 2006

This paper demonstrates implementation of some CDMA system compatible antenna array algorithms namely LMS and space code correlator (SCC) on an FPGA. A comparative study of FPGA and DSP implementation issues such as architecture complexity and weight vector computation time is also given. The implementations of the algorithms are performed on Xilinx Virtex II Pro FPGA and Texas Instruments (TI) TMS32OC67x floating-point DSP platforms. For the signal modeling, cdma2000 reverse link signal model is considered for uniform linear array topology and varying multipath propagation conditions. Results show that the both algorithms, which were implemented on Xilinx XC2VP4 and TMS320C6713 DSP, provides weight vector computation time smaller than 10 ms period.