Design and fabrication of high current AlGaN/GaN HFET for Gen III solid state transformer

Ji, In−Hwan; Wang, Sizhen; Lee, Bongmook; Ke, Haotao; Misra, Veena; Huang, Alex Q.

doi:10.1109/wipda.2014.6964625

Cited by 5 publications

(1 citation statement)

References 1 publication

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“…Using a combination of different switching devices is also possible. Reference [64] suggested the use of GaN devices instead of MOSFET at the low voltage inverter stage, which increases the overall efficiency as GaN devices have lower conduction resistance. Alternatively, in [65], gate turn off thyristors (GTOs) were used for the HV rectifier for the sake of lower cost, but the disadvantage of using GTOs is the increased injected harmonics into the grid.…”

Section: High Voltage Solid State Transformersmentioning

confidence: 99%

Solid State Transformers Topologies, Controllers, and Applications: State-of-the-Art Literature Review

2018

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With the global trend to produce clean electrical energy, the penetration of renewable energy sources in existing electricity infrastructure is expected to increase significantly within the next few years. The solid state transformer (SST) is expected to play an essential role in future smart grid topologies. Unlike traditional magnetic transformer, SST is flexible enough to be of modular construction, enabling bi-directional power flow and can be employed for AC and DC grids. Moreover, SSTs can control the voltage level and modulate both active and reactive power at the point of common coupling without the need to external flexible AC transmission system device as per the current practice in conventional electricity grids. The rapid advancement in power semiconductors switching speed and power handling capacity will soon allow for the commercialisation of grid-rated SSTs. This paper is aimed at introducing a state-of-the-art review for SST proposed topologies, controllers, and applications. Additionally, strengths, weaknesses, opportunities, and threats (SWOT) analysis along with a brief review of market drivers for prospective commercialisation are elaborated.

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Section: High Voltage Solid State Transformersmentioning

confidence: 99%

Solid State Transformers Topologies, Controllers, and Applications: State-of-the-Art Literature Review

2018

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Fabrication and Switching Performance of 8 A–500 V D‐Mode GaN MISHEMTs

Baby,

Roy,

Tripathy

et al. 2023

Physica Status Solidi (a)

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In this work, the design, fabrication, static device testing, and double‐pulse switching performance of multi‐finger D‐mode GaN metal–insulator–semiconductor high‐electron‐mobility transistors (MISHEMTs) on silicon are discussed. Utilizing an metal‐organic chemical vapor deposition‐grown GaN high‐electron‐mobility transistors stack with a superlattice buffer, field‐plated devices with a meandering gate geometry and a total gate width of 30 mm are fabricated. Plasma enhanced chemical vapor deposition SiNx is used as the gate dielectric, followed by an optimized bilayer SiNx passivation scheme. Devices with 100 μm gate width have an ON/OFF ratio of ≈108. They are analyzed for dynamic Ron (normalized Ron = 3 at 100 μs) and time‐dependent dielectric breakdown for gate reliability, resulting in a β value of 2.65 from the Weibull plot. Devices with a 30 mm gate width exhibit a maximum ON current of 8 A at zero gate voltage and a three‐terminal breakdown of ≈500 V. The devices are diced, wire‐bonded to a printed circuit board, and a double‐pulsed test is performed for switching transient characterization under clamped inductive load. The OFF‐state and ON‐state energy loss are estimated to be Eon = 14 μJ and EOFF = 27 μJ, respectively, when switched at 5 A, 50 V. In this study, the potential of GaN MISHEMTs with bilayer SiNx passivation for low‐power D‐mode switching applications (5 A, 50 V) is demonstrated.

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Physical design guidelines to minimize area-specific ON-resistance for rated ON-current and breakdown voltage of GaN power HEMTs

Khan¹,

Muralidharan²,

Chandrasekar³

2023

Semicond. Sci. Technol.

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In this article, we report on the development of an analytical model to estimate area-specific ON-state resistance (RON) of GaN-based power high electron mobility transistor (HEMT) using rated device specifications – ON-state drain current (ION) and maximum operating drain-to-source voltage (VDSO) – as input parameters. The rated ION and VDSO are considered as fractions k and S, of the maximum possible drain current (IDS,max) and breakdown voltage (VBR), respectively, deliverable by the power device. The developed model is utilized to obtain the optimal physical design space parameters including unit gate width (W), number of unit gate fingers (N), source and drain electrode widths (L) and thickness (t), for a comb-like power HEMT design. Due consideration has been given to the trade-off between RON and area-specific RON of the transistor, and device processing limitations for all these parameters and the model has been benchmarked to experimental results. Our calculations impose a lower-bound for the best possible RON as well as the area-specific on-resistance product (RON × AA) that can be obtained for a given starting channel sheet resistance in the comb architecture for a desired ION – VDSO rating.

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Design and fabrication of high current AlGaN/GaN HFET for Gen III solid state transformer

Cited by 5 publications

References 1 publication

Solid State Transformers Topologies, Controllers, and Applications: State-of-the-Art Literature Review

Solid State Transformers Topologies, Controllers, and Applications: State-of-the-Art Literature Review

Fabrication and Switching Performance of 8 A–500 V D‐Mode GaN MISHEMTs

Physical design guidelines to minimize area-specific ON-resistance for rated ON-current and breakdown voltage of GaN power HEMTs

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