Physical design guidelines to minimize area-specific ON-resistance for rated ON-current and breakdown voltage of GaN power HEMTs

Abstract

In this article, we report on the development of an analytical model to estimate area-specific ON-state resistance (RON) of GaN-based power high electron mobility transistor (HEMT) using rated device specifications – ON-state drain current (ION) and maximum operating drain-to-source voltage (VDSO) – as input parameters. The rated ION and VDSO are considered as fractions k and S, of the maximum possible drain current (IDS,max) and breakdown voltage (VBR), respectively, deliverable by the power device. The developed model is utilized to obtain the optimal physical design space parameters including unit gate width (W), number of unit gate fingers (N), source and drain electrode widths (L) and thickness (t), for a comb-like power HEMT design. Due consideration has been given to the trade-off between RON and area-specific RON of the transistor, and device processing limitations for all these parameters and the model has been benchmarked to experimental results. Our calculations impose a lower-bound for the best possible RON as well as the area-specific on-resistance product (RON × AA) that can be obtained for a given starting channel sheet resistance in the comb architecture for a desired ION – VDSO rating.