Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits

Moaiyeri, Mohammad Hossein; Rahi, Afshin; Sharifi, Fazel; Navi, Keivan

doi:10.1016/j.jart.2016.12.006

Cited by 29 publications

(10 citation statements)

References 20 publications

(22 reference statements)

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“…Three different SWCNT behaviors are determined by the chiral vector: a) the zigzag nanotube, when n 1 = 0 or n 2 = 0; b) the armchair nanotube when n 1 = n 2 and c) the chiral nanotube when n 1 = n 2 = 0. The electricity conducting attribute of the SWCNT is based on the chiral vector, behaving as a semiconductor if the two indexes n 1 and n 2 fit the relation n 1 − n 2 = 3i (where i is an integer) [9].…”

Section: Cntfet Technology and Mvl Circuits Review A Carbon Nanomentioning

confidence: 99%

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

2020

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The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

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Section: Cntfet Technology and Mvl Circuits Review A Carbon Nanomentioning

confidence: 99%

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

2020

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“…Figure 1 shows the 3-D structure of the CNFET. 10,17 As graphene tubes have very high electron mobility and conductivity, therefore drain current remains approximately constant throughout the channel. Figure 2 shows the cross-sectional view of CNFET.…”

Section: Introductionmentioning

confidence: 99%

“…The width of the channel can be expanded by increasing the number of CNTs among source and channel. 10 Depending upon the number of carbon layers, the carbon nanotubes can be classified as single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs). L d , L ch, and L s are the lengths of drain, channel and source respectively.…”

Section: Introductionmentioning

confidence: 99%

“…Since graphene has very low electrical resistivity, therefore the movement of electrons in CNT takes place through the ballistic transport in a medium having very low resistivity. 10,17 As graphene tubes have very high electron mobility and conductivity, therefore drain current remains approximately constant throughout the channel. CNFET have very high speed and lower power consumption in comparison with MOSFET due to its negligible resistivity.…”

Section: Introductionmentioning

confidence: 99%

“…SWCNT consists of a single graphene sheet wrapped in the form of the cylinder while MWCNT comprises of an array of concentric nanotubes nested like rings of the tree trunk. 10 Depending upon the number of carbon layers, the carbon nanotubes can be classified as single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs). Single-walled CNTs are formed by rolling a single graphene sheet to form a cylindrical wall while multi-walled CNTs have many such single-walled cylinders that are stacked inside one another.…”

Section: Introductionmentioning

confidence: 99%

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A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adderdesigned using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder. K E Y W O R D SCNFET, Domino, Dynamic, FOM, VLSI

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Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

Khurshid,

Singh

2024

Circuit Theory & Apps

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SummaryMultivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%.

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Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits

Cited by 29 publications

References 20 publications

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

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