Design and design methods for unified multiplier and inverter and its application for HECC

Fan, Junfeng; Batina, Lejla; Verbauwhede, Ingrid

doi:10.1016/j.vlsi.2011.04.001

Cited by 12 publications

(3 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hence, both PM and PA are performed in every iteration. Therefore, Algorithm 2 is secure in resistant timing attacks and simple power analysis attacks due to the independence between the operation and the value of scalar k. Meanwhile, we optimize the modular inversion and modular multiplication algorithms to make the operation time constant to resist timing attacks [32]. Overall, Algorithm 2 makes the proposed ECC processor resistant against simple sidechannel attacks (while other types of side-channel attacks are beyond the scope of this paper).…”

Section: Proposed Ld Montgomery Algorithmmentioning

confidence: 99%

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor

et al. 2022

View full text Add to dashboard Cite

Along with the rapid development in security technology, the efficient implementation of a large field-size elliptic curve cryptosystem (ECC) is becoming demanding in many critical applications as small-sized cryptosystems are gradually becoming obsolete. Based on this consideration, this paper proposes a series of novel coherent interdependence efforts to propose a novel implementation of ECC hardware cryptoprocessor: (i) We firstly propose a new Montgomery point multiplication (PM) algorithm to optimize and balance the signal flow and resource utilization efficiency; (ii) Then, we have efficiently constructed a new ECC processor over GF (2 m ) (with the support of a series of algorithm-architecture coimplementation techniques); (iii) Finally, we have given detailed comparison and performance analysis to show that the proposed cryptographic processor has superior performance than the competing designs, i.e., smaller area-delay product (ADP) than the competing designs. The proposed large field-size ECC processor (and the proposed design strategy) can be extended and applied in many security-demanding applications.INDEX TERMS Elliptic curve cryptography, FPGA, hardware design, large field-size, low-complexity, point multiplication.

show abstract

Section: Proposed Ld Montgomery Algorithmmentioning

confidence: 99%

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor

et al. 2022

View full text Add to dashboard Cite

show abstract

“…Therefore, there are many algorithms are presented in the literature to perform field division with their high performance realization in both software and hardware. These algorithms can be computed based on several schemes such as Fermat's little theorem [1,2], Extended Euclid's algorithm (EEA) [3,4,5,6,7], and Extended Stein's algorithm (ESA) [8,9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

“…There are two hardware techniques used to implement the filed division algorithms. The first technique is the conventional technique that is based on Lookup tables and is efficient for VLSI implementation of field division algorithms over GF(2 m ) for small field size m [3,6]. When m gets larger, we can not easily use this technique in VLSI implementations due to the increasing overhead cost of area.…”

Section: Introductionmentioning

confidence: 99%

New systolic array architecture for finite field division

Ibrahim

Elsimary

Gebali

2018

IEICE Electron. Express

View full text Add to dashboard Cite

This paper proposes a new systolic array architecture to perform division operations over GF(2 m ) based on the modified Stein's algorithm. The systolic structure is extracted by applying a regular approach to the division algorithm. This approach starts by obtaining the dependency graph for the intended algorithm and assigning a time value to each node in the dependency graph using a scheduling function and ends by projecting several nodes of the dependency graph to a processing element to constitute the systolic array. The obtained design structure has the advantage of reducing the number of flip-flops required to store the intermediate variables of the algorithm and hence reduces the total gate counts to a large extent compared to the other related designs. The analytical results show that the proposed design outperforms the related designs in terms of area (at least 32% reduction in area) and speed (at least 60% reduction in the total computation time) and has the lowest AT complexity that ranges from 80% to 94%.

show abstract

Unified systolic array architecture for finite field multiplication and inversion

Ibrahim

Al-Somani

Gebali

2017

Computers & Electrical Engineering

View full text Add to dashboard Cite

Design and design methods for unified multiplier and inverter and its application for HECC

Cited by 12 publications

References 34 publications

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor

New systolic array architecture for finite field division

Unified systolic array architecture for finite field multiplication and inversion

Contact Info

Product

Resources

About